b68d23da3c
In previous implementation, it was known that it does not perform full reset, and that some peripherals, such as GLB core, which handles among other stuff GPIOs, was not reset. It was presumed, that full reset by software is not possible, although, by accident, even when comment says that CTRL_PWRON_RESET is set to 1, it is not (value written into 0x40000018 supposed to be 0x7, not 0x6). CTRL_PWRON_RESET indeed triggers full "power-on like" reset, so this method is implemented in this commit. There are some workarounds to make reset seamless, without any error messages, which are described in comments of TCL script. Only down-side of this reset is, that chip is halted after reset bit later in BootROM than previous implementation, but it's still good. Change-Id: Ife2cdcc6a2d96a2e24039bfec149705baf046318 Signed-off-by: Marek Kraus <gamelaster@outlook.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8529 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
74 lines
2.1 KiB
INI
74 lines
2.1 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# Bouffalo Labs BL702, BL704 and BL706 target
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#
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# https://en.bouffalolab.com/product/?type=detail&id=8
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#
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# Default JTAG pins: (if not changed by eFuse configuration)
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# TMS - GPIO0
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# TDI - GPIO1
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# TCK - GPIO2
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# TDO - GPIO9
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#
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source [find mem_helper.tcl]
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transport select jtag
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME bl702
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}
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jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000e05
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME riscv -chain-position $_TARGETNAME
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riscv set_mem_access sysbus
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$_TARGETNAME configure -work-area-phys 0x22020000 -work-area-size 0x10000 -work-area-backup 1
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# Internal RC ticks on 32 MHz, so this speed should be safe to use.
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adapter speed 4000
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# Debug Module's ndmreset resets only Trust Zone Controller, so we need to do SW reset instead.
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# CTRL_PWRON_RESET triggers full "power-on like" reset.
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# This means that pinmux configuration to access JTAG is reset as well, and configured back early
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# in BootROM.
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$_TARGETNAME configure -event reset-assert-pre {
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halt
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# Switch clock to internal RC32M
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# In HBN_GLB, set ROOT_CLK_SEL = 0
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mmw 0x4000f030 0x0 0x00000003
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# Wait for clock switch
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sleep 10
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# GLB_REG_BCLK_DIS_FALSE
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mww 0x40000ffc 0x0
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# HCLK is RC32M, so BCLK/HCLK doesn't need divider
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# In GLB_CLK_CFG0, set BCLK_DIV = 0 and HCLK_DIV = 0
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mmw 0x40000000 0x0 0x00FFFF00
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# Wait for clock to stabilize
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sleep 10
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# Do reset
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# In GLB_SWRST_CFG2, clear CTRL_SYS_RESET, CTRL_CPU_RESET and CTRL_PWRON_RESET
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mmw 0x40000018 0x0 0x00000007
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# Since this full software reset resets GPIO pinmux as well, we will lose access
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# to JTAG right away after writing to register. This chip doesn't support abstract
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# memory access, so when this is done by progbuf or sysbus, OpenOCD will fail to read
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# if write was successful or not, and will print error about that. Since receiving of
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# this error is expected, we will turn off log printing for a moment,
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set lvl [lindex [debug_level] 1]
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debug_level -1
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# In GLB_SWRST_CFG2, set CTRL_SYS_RESET, CTRL_CPU_RESET and CTRL_PWRON_RESET to 1
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catch {mmw 0x40000018 0x7 0x0}
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debug_level $lvl
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}
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