5706fd7860
Stash a pointer to the CPSR in the "struct arm", to help get rid of the (common) references to its index in the register cache. This removes almost all references to CPSR offsets outside of the toplevel ARM code ... except a pair related to the current ARM11 "simulator" logic (which should be removable soonish). This is a net minor code shrink of a few hundred bytes of object code, and also makes the code more readable. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
108 lines
3.2 KiB
C
108 lines
3.2 KiB
C
/***************************************************************************
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* Copyright (C) 2009 by David Brownell *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifndef ARMV7A_H
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#define ARMV7A_H
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#include "arm_adi_v5.h"
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#include "armv4_5.h"
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#include "armv4_5_mmu.h"
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#include "armv4_5_cache.h"
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enum
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{
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ARM_PC = 15,
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ARM_CPSR = 16
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}
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;
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#define ARMV7_COMMON_MAGIC 0x0A450999
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/* VA to PA translation operations opc2 values*/
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#define V2PCWPR 0
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#define V2PCWPW 1
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#define V2PCWUR 2
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#define V2PCWUW 3
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#define V2POWPR 4
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#define V2POWPW 5
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#define V2POWUR 6
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#define V2POWUW 7
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struct armv7a_common
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{
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struct arm armv4_5_common;
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int common_magic;
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struct reg_cache *core_cache;
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/* arm adp debug port */
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struct swjdp_common swjdp_info;
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/* Core Debug Unit */
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uint32_t debug_base;
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uint8_t debug_ap;
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uint8_t memory_ap;
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/* Cache and Memory Management Unit */
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struct armv4_5_mmu_common armv4_5_mmu;
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int (*read_cp15)(struct target *target,
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uint32_t op1, uint32_t op2,
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uint32_t CRn, uint32_t CRm, uint32_t *value);
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int (*write_cp15)(struct target *target,
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uint32_t op1, uint32_t op2,
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uint32_t CRn, uint32_t CRm, uint32_t value);
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int (*examine_debug_reason)(struct target *target);
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void (*post_debug_entry)(struct target *target);
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void (*pre_restore_context)(struct target *target);
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void (*post_restore_context)(struct target *target);
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};
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static inline struct armv7a_common *
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target_to_armv7a(struct target *target)
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{
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return container_of(target->arch_info, struct armv7a_common,
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armv4_5_common);
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}
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struct armv7a_algorithm
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{
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int common_magic;
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enum armv4_5_mode core_mode;
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enum armv4_5_state core_state;
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};
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struct armv7a_core_reg
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{
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int num;
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enum armv4_5_mode mode;
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struct target *target;
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struct armv7a_common *armv7a_common;
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};
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int armv7a_arch_state(struct target *target);
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struct reg_cache *armv7a_build_reg_cache(struct target *target,
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struct armv7a_common *armv7a_common);
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int armv7a_register_commands(struct command_context *cmd_ctx);
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int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a);
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#endif /* ARMV4_5_H */
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