Matthias Welwarsky
bf1efe05bb
This patch contains a major overhaul of the target run control, mainly for the sake of satisfying gdbs ideas of how a target should respond to various control requests for the debugger. The changes allow gdb a slightly better control on how cores are stepped: a core can be single-stepped while other cores remain halted or continue normal execution until the single-stepped core halts again. Also, on any halting event (user command or breakpoint) the system is brought into a stable state with all cores halted before the halt is signaled to the debugger. This patch also transitions the target code to make use of the new CTI abstraction instead of accessing CTI registers directly. Change-Id: I8ddc9abb119e04580d671b57ee12240c3f5070a0 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3993 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
123 lines
3.9 KiB
C
123 lines
3.9 KiB
C
/*
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* Copyright (C) 2009 by David Brownell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef OPENOCD_TARGET_ARMV8_DPM_H
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#define OPENOCD_TARGET_ARMV8_DPM_H
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#include "arm_dpm.h"
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/* forward-declare struct armv8_common */
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struct armv8_common;
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/**
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* This wraps an implementation of DPM primitives. Each interface
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* provider supplies a structure like this, which is the glue between
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* upper level code and the lower level hardware access.
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*
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* It is a PRELIMINARY AND INCOMPLETE set of primitives, starting with
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* support for CPU register access.
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*/
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int armv8_dpm_setup(struct arm_dpm *dpm);
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int armv8_dpm_initialize(struct arm_dpm *dpm);
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int armv8_dpm_read_current_registers(struct arm_dpm *);
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int armv8_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode);
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int armv8_dpm_write_dirty_registers(struct arm_dpm *, bool bpwp);
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void armv8_dpm_report_wfar(struct arm_dpm *, uint64_t wfar);
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/* DSCR bits; see ARMv7a arch spec section C10.3.1.
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* Not all v7 bits are valid in v6.
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*/
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#define DSCR_DEBUG_STATUS_MASK (0x1F << 0)
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#define DSCR_ERR (0x1 << 6)
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#define DSCR_SYS_ERROR_PEND (0x1 << 7)
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#define DSCR_CUR_EL (0x3 << 8)
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#define DSCR_EL_STATUS_MASK (0xF << 10)
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#define DSCR_HDE (0x1 << 14)
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#define DSCR_SDD (0x1 << 16)
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#define DSCR_NON_SECURE (0x1 << 18)
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#define DSCR_MA (0x1 << 20)
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#define DSCR_TDA (0x1 << 21)
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#define DSCR_INTDIS_MASK (0x3 << 22)
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#define DSCR_ITE (0x1 << 24)
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#define DSCR_PIPE_ADVANCE (0x1 << 25)
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#define DSCR_TXU (0x1 << 26)
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#define DSCR_RTO (0x1 << 27) /* bit 28 is reserved */
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#define DSCR_ITO (0x1 << 28)
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#define DSCR_DTR_TX_FULL (0x1 << 29)
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#define DSCR_DTR_RX_FULL (0x1 << 30) /* bit 31 is reserved */
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/* Methods of entry into debug mode */
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#define DSCRV8_ENTRY_NON_DEBUG (0x2)
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#define DSCRV8_ENTRY_RESTARTING (0x1)
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#define DSCRV8_ENTRY_BKPT (0x7)
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#define DSCRV8_ENTRY_EXT_DEBUG (0x13)
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#define DSCRV8_ENTRY_HALT_STEP_NORMAL (0x1B)
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#define DSCRV8_ENTRY_HALT_STEP_EXECLU (0x1F)
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#define DSCRV8_ENTRY_OS_UNLOCK (0x23)
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#define DSCRV8_ENTRY_RESET_CATCH (0x27)
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#define DSCRV8_ENTRY_WATCHPOINT (0x2B)
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#define DSCRV8_ENTRY_HLT (0x2F)
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#define DSCRV8_ENTRY_SW_ACCESS_DBG (0x33)
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#define DSCRV8_ENTRY_EXCEPTION_CATCH (0x37)
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#define DSCRV8_ENTRY_HALT_STEP (0x3B)
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#define DSCRV8_HALT_MASK (0x3C)
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/*DRCR registers*/
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#define DRCR_CSE (1 << 2)
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#define DRCR_CSPA (1 << 3)
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#define DRCR_CBRRQ (1 << 4)
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/* DTR modes */
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#define DSCR_EXT_DCC_NON_BLOCKING (0x0 << 20)
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#define DSCR_EXT_DCC_STALL_MODE (0x1 << 20)
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#define DSCR_EXT_DCC_FAST_MODE (0x2 << 20) /* bits 22, 23 are reserved */
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/* DRCR (debug run control register) bits */
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#define DRCR_HALT (1 << 0)
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#define DRCR_RESTART (1 << 1)
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#define DRCR_CLEAR_EXCEPTIONS (1 << 2)
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/* PRSR (processor debug status register) bits */
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#define PRSR_PU (1 << 0)
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#define PRSR_SPD (1 << 1)
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#define PRSR_RESET (1 << 2)
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#define PRSR_SR (1 << 3)
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#define PRSR_HALT (1 << 4)
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#define PRSR_OSLK (1 << 5)
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#define PRSR_DLK (1 << 6)
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#define PRSR_EDAD (1 << 7)
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#define PRSR_SDAD (1 << 8)
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#define PRSR_EPMAD (1 << 9)
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#define PRSR_SPMAD (1 << 10)
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#define PRSR_SDR (1 << 11)
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/* PRCR (processor debug control register) bits */
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#define PRCR_CORENPDRQ (1 << 0)
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#define PRCR_CWRR (1 << 2)
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#define PRCR_COREPURQ (1 << 3)
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void armv8_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dcsr);
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void armv8_dpm_handle_exception(struct arm_dpm *dpm);
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enum arm_state armv8_dpm_get_core_state(struct arm_dpm *dpm);
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#endif /* OPENOCD_TARGET_ARM_DPM_H */
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