In previous implementation, it was known that it does not perform
full reset, and that some peripherals, such as GLB core,
which handles among other stuff GPIOs, was not reset.
It was presumed, that full reset by software is not possible,
although, by accident, even when comment says that
CTRL_PWRON_RESET is set to 1, it is not
(value written into 0x40000018 supposed to be 0x7, not 0x6).
CTRL_PWRON_RESET indeed triggers full "power-on like" reset,
so this method is implemented in this commit.
There are some workarounds to make reset seamless, without any
error messages, which are described in comments of TCL script.
Only down-side of this reset is, that chip is halted after reset
bit later in BootROM than previous implementation,
but it's still good.
Change-Id: Ife2cdcc6a2d96a2e24039bfec149705baf046318
Signed-off-by: Marek Kraus <gamelaster@outlook.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8529
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
# SPDX-License-Identifier: GPL-2.0-or-later
Prerequisites:
The users of OpenOCD as well as computer programs interacting with OpenOCD are expecting that certain commands
do the same thing across all the targets.
Rules to follow when writing scripts:
1. The configuration script should be defined such as , for example, the following sequences are working:
reset
flash info <bank>
and
reset
flash erase_address <start> <len>
and
reset init
load
In most cases this can be accomplished by specifying the default startup mode as reset_init (target command
in the configuration file).
2. If the target is correctly configured, flash must be writable without any other helper commands. It is
assumed that all write-protect mechanisms should be disabled.
3. The configuration scripts should be defined such as the binary that was written to flash verifies
(turn off remapping, checksums, etc...)
flash write_image [file] <parameters>
verify_image [file] <parameters>
4. adapter speed sets the maximum speed (or alternatively RCLK). If invoked
multiple times only the last setting is used.
interface/xxx.cfg files are always executed *before* target/xxx.cfg
files, so any adapter speed in interface/xxx.cfg will be overridden by
target/xxx.cfg. adapter speed in interface/xxx.cfg would then, effectively,
set the default JTAG speed.
Note that a target/xxx.cfg file can invoke another target/yyy.cfg file,
so one can create target subtype configurations where e.g. only
amount of DRAM, oscillator speeds differ and having a single
config file for the default/common settings.
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