Adds all parts. Schematic almost done. first layout.

This commit is contained in:
Pbopbo
2026-02-23 16:34:04 +01:00
parent 32afe94da0
commit 176d7c4d63
15 changed files with 99348 additions and 286 deletions

View File

@@ -48,11 +48,34 @@
"silk_text_thickness": 0.1,
"silk_text_upright": false,
"zones": {
"min_clearance": 0.5
"min_clearance": 0.4
}
},
"diff_pair_dimensions": [],
"drc_exclusions": [],
"diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [
[
"hole_clearance|214490000|132155000|a725debd-1204-4326-89a6-ac420bab6f87|deb49b5d-0a3e-4721-b56e-2c0eff4722d2",
""
],
[
"hole_clearance|214490000|132155000|a725debd-1204-4326-89a6-ac420bab6f87|e6e74e5d-1677-4ec6-9e5e-80648b6005af",
""
],
[
"hole_clearance|214490000|138255000|64a1c56c-519d-4531-b1b9-4852373d497e|3684f726-2f11-46b6-82b2-efc50d9af233",
""
],
[
"hole_clearance|214490000|138255000|64a1c56c-519d-4531-b1b9-4852373d497e|dc86d469-251b-44ae-9cd6-2730ed38daaf",
""
]
],
"meta": {
"version": 2
},
@@ -131,8 +154,8 @@
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.0,
"min_via_annular_width": 0.1,
"min_via_diameter": 0.5,
"min_via_annular_width": 0.05,
"min_via_diameter": 0.3,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
@@ -180,7 +203,11 @@
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [],
"track_widths": [
0.0,
0.0,
0.0
],
"tuning_pattern_settings": {
"diff_pair_defaults": {
"corner_radius_percentage": 80,
@@ -207,7 +234,16 @@
"spacing": 0.6
}
},
"via_dimensions": [],
"via_dimensions": [
{
"diameter": 0.0,
"drill": 0.0
},
{
"diameter": 0.4,
"drill": 0.3
}
],
"zones_allow_external_fillets": false
},
"ipc2581": {
@@ -473,6 +509,13 @@
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6
},
{
"name": "Power",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 0,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 2.0
}
],
"meta": {
@@ -480,7 +523,12 @@
},
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
"netclass_patterns": [
{
"netclass": "Power",
"pattern": "+5V"
}
]
},
"pcbnew": {
"last_paths": {