Finishes routing, no DRC errors anymore.

This commit is contained in:
Pbopbo
2025-12-15 12:19:08 +01:00
parent c47a6ceed1
commit fe5a4bd457
20 changed files with 130026 additions and 6161 deletions

View File

@@ -51,16 +51,22 @@
"min_clearance": 0.5
}
},
"diff_pair_dimensions": [],
"diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [],
"meta": {
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"annular_width": "ignore",
"clearance": "ignore",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_edge_clearance": "ignore",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"creepage": "error",
@@ -73,7 +79,7 @@
"footprint_filters_mismatch": "ignore",
"footprint_symbol_mismatch": "warning",
"footprint_type_mismatch": "ignore",
"hole_clearance": "error",
"hole_clearance": "ignore",
"hole_to_hole": "warning",
"holes_co_located": "warning",
"invalid_outline": "error",
@@ -99,7 +105,7 @@
"silk_overlap": "warning",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
"starved_thermal": "ignore",
"text_height": "warning",
"text_on_edge_cuts": "error",
"text_thickness": "warning",
@@ -131,8 +137,8 @@
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.0,
"min_via_annular_width": 0.1,
"min_via_diameter": 0.5,
"min_via_annular_width": 0.075,
"min_via_diameter": 0.45,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
@@ -180,7 +186,11 @@
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [],
"track_widths": [
0.0,
0.2,
0.3
],
"tuning_pattern_settings": {
"diff_pair_defaults": {
"corner_radius_percentage": 80,
@@ -207,7 +217,12 @@
"spacing": 0.6
}
},
"via_dimensions": [],
"via_dimensions": [
{
"diameter": 0.0,
"drill": 0.0
}
],
"zones_allow_external_fillets": false
},
"ipc2581": {
@@ -458,7 +473,7 @@
"classes": [
{
"bus_width": 12,
"clearance": 0.2,
"clearance": 0.125,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
@@ -467,30 +482,70 @@
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": -1,
"priority": 2147483647,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.2,
"via_diameter": 0.6,
"track_width": 0.125,
"via_diameter": 0.45,
"via_drill": 0.3,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.2,
"name": "3v3",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 0,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.3
},
{
"bus_width": 12,
"clearance": 0.125,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "All Nets",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": -1,
"priority": 5,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.2,
"via_diameter": 0.6,
"track_width": 0.125,
"via_diameter": 0.45,
"via_drill": 0.3,
"wire_width": 6
},
{
"clearance": 0.2,
"name": "ground",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 3,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.3
},
{
"clearance": 0.2,
"diff_pair_gap": 0.2,
"diff_pair_width": 0.2644,
"name": "usb_90r",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 4,
"schematic_color": "rgba(0, 0, 0, 0.000)"
},
{
"clearance": 0.2,
"name": "vbat",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 1,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.3
},
{
"clearance": 0.2,
"name": "vbus",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 2,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.3
}
],
"meta": {
@@ -498,7 +553,44 @@
},
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
"netclass_patterns": [
{
"netclass": "usb_90r",
"pattern": "/D_N"
},
{
"netclass": "usb_90r",
"pattern": "/D_P"
},
{
"netclass": "ground",
"pattern": "GND"
},
{
"netclass": "vbus",
"pattern": "VBUS"
},
{
"netclass": "vbus",
"pattern": "/VBUS_DOCK"
},
{
"netclass": "vbat",
"pattern": "/VBAT_CON"
},
{
"netclass": "vbat",
"pattern": "VBAT"
},
{
"netclass": "3v3",
"pattern": "3V3"
},
{
"netclass": "3v3",
"pattern": "/3V3SPK"
}
]
},
"pcbnew": {
"last_paths": {