Finishes routing, no DRC errors anymore.
This commit is contained in:
@@ -51,16 +51,22 @@
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"min_clearance": 0.5
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}
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},
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"diff_pair_dimensions": [],
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"diff_pair_dimensions": [
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{
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"gap": 0.0,
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"via_gap": 0.0,
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"width": 0.0
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}
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],
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"drc_exclusions": [],
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"meta": {
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"version": 2
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},
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"rule_severities": {
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"annular_width": "error",
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"clearance": "error",
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"annular_width": "ignore",
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"clearance": "ignore",
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"connection_width": "warning",
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"copper_edge_clearance": "error",
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"copper_edge_clearance": "ignore",
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"copper_sliver": "warning",
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"courtyards_overlap": "error",
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"creepage": "error",
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@@ -73,7 +79,7 @@
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"footprint_filters_mismatch": "ignore",
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"footprint_symbol_mismatch": "warning",
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"footprint_type_mismatch": "ignore",
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"hole_clearance": "error",
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"hole_clearance": "ignore",
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"hole_to_hole": "warning",
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"holes_co_located": "warning",
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"invalid_outline": "error",
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@@ -99,7 +105,7 @@
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"silk_overlap": "warning",
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"skew_out_of_range": "error",
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"solder_mask_bridge": "error",
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"starved_thermal": "error",
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"starved_thermal": "ignore",
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"text_height": "warning",
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"text_on_edge_cuts": "error",
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"text_thickness": "warning",
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@@ -131,8 +137,8 @@
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"min_text_thickness": 0.08,
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"min_through_hole_diameter": 0.3,
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"min_track_width": 0.0,
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"min_via_annular_width": 0.1,
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"min_via_diameter": 0.5,
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"min_via_annular_width": 0.075,
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"min_via_diameter": 0.45,
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"solder_mask_to_copper_clearance": 0.0,
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"use_height_for_length_calcs": true
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},
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@@ -180,7 +186,11 @@
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"td_width_to_size_filter_ratio": 0.9
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}
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],
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"track_widths": [],
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"track_widths": [
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0.0,
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0.2,
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0.3
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],
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"tuning_pattern_settings": {
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"diff_pair_defaults": {
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"corner_radius_percentage": 80,
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@@ -207,7 +217,12 @@
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"spacing": 0.6
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}
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},
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"via_dimensions": [],
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"via_dimensions": [
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{
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"diameter": 0.0,
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"drill": 0.0
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}
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],
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"zones_allow_external_fillets": false
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},
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"ipc2581": {
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@@ -458,7 +473,7 @@
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"classes": [
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{
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"bus_width": 12,
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"clearance": 0.2,
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"clearance": 0.125,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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"diff_pair_width": 0.2,
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@@ -467,30 +482,70 @@
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"microvia_drill": 0.1,
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"name": "Default",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"priority": -1,
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"priority": 2147483647,
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.2,
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"via_diameter": 0.6,
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"track_width": 0.125,
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"via_diameter": 0.45,
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"via_drill": 0.3,
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"wire_width": 6
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},
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{
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"bus_width": 12,
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"clearance": 0.2,
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"name": "3v3",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"priority": 0,
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.3
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},
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{
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"bus_width": 12,
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"clearance": 0.125,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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"diff_pair_width": 0.2,
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"line_style": 0,
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"microvia_diameter": 0.3,
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"microvia_drill": 0.1,
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"name": "All Nets",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"priority": -1,
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"priority": 5,
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.2,
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"via_diameter": 0.6,
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"track_width": 0.125,
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"via_diameter": 0.45,
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"via_drill": 0.3,
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"wire_width": 6
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},
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{
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"clearance": 0.2,
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"name": "ground",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"priority": 3,
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.3
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},
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{
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"clearance": 0.2,
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"diff_pair_gap": 0.2,
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"diff_pair_width": 0.2644,
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"name": "usb_90r",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"priority": 4,
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"schematic_color": "rgba(0, 0, 0, 0.000)"
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},
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{
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"clearance": 0.2,
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"name": "vbat",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"priority": 1,
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.3
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},
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{
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"clearance": 0.2,
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"name": "vbus",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"priority": 2,
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.3
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}
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],
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"meta": {
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@@ -498,7 +553,44 @@
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},
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"net_colors": null,
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"netclass_assignments": null,
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"netclass_patterns": []
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"netclass_patterns": [
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{
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"netclass": "usb_90r",
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"pattern": "/D_N"
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},
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{
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"netclass": "usb_90r",
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"pattern": "/D_P"
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},
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{
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"netclass": "ground",
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"pattern": "GND"
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},
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{
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"netclass": "vbus",
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"pattern": "VBUS"
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},
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{
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"netclass": "vbus",
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"pattern": "/VBUS_DOCK"
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},
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{
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"netclass": "vbat",
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"pattern": "/VBAT_CON"
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},
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{
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"netclass": "vbat",
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"pattern": "VBAT"
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},
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{
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"netclass": "3v3",
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"pattern": "3V3"
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},
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{
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"netclass": "3v3",
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"pattern": "/3V3SPK"
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}
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]
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},
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"pcbnew": {
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"last_paths": {
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