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- added debug output for D/I FSR and FAR (arm920t)

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- fixed bug that caused CPSR to be corrupted in Thumb mode


git-svn-id: svn://svn.berlios.de/openocd/trunk@93 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
drath
2006-09-04 10:31:28 +00:00
parent e2e5917109
commit 028f59ede5
4 changed files with 35 additions and 15 deletions
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13
src/target/armv4_5.h
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@@ -229,6 +229,17 @@ extern int armv4_5_invalidate_core_regs(target_t *target);
*/
#define ARMV4_5_T_LDR(Rd, Rn) ((0x6800 | (Rn << 3) | Rd) | ((0x6800 | (Rn << 3) | Rd) << 16))
/* Load multiple (Thumb state)
* Rn: base register
* List: for each bit in list: store register
*/
#define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | (Rn << 8) | List) | ((0xc800 | (Rn << 8) | List) << 16))
/* Load register with PC relative addressing
* Rd: register to load
*/
#define ARMV4_5_T_LDR_PCREL(Rd) ((0x4800 | (Rd << 8)) | ((0x4800 | (Rd << 8)) << 16))
/* Move hi register (Thumb mode)
* Rd: destination register
* Rm: source register
@@ -237,7 +248,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target);
/* No operation (Thumb mode)
*/
#define ARMV4_5_T_NOP (0x1c3f | (0x1c3f << 16))
#define ARMV4_5_T_NOP (0x46c0 | (0x46c0 << 16))
/* Move immediate to register (Thumb state)
* Rd: destination register