forked from auracaster/openocd
xscale: Move debug handler to contrib/loaders
Avoid special rules to generate array at compile time by shipping the generated file. Convert to Makefile build like the other loaders. Change-Id: I5a05edddcfaff3d395086cd3aa33120f8a7aa9dc Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3864 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This commit is contained in:
Andreas Fritiofson
committed by
Paul Fertser
Paul Fertser
parent
cdba6ba0ad
commit
1039ed3ff2
@@ -9,19 +9,6 @@ endif
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SUBDIRS = openrisc
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libtarget_la_LIBADD = $(top_builddir)/src/target/openrisc/libopenrisc.la
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BIN2C = $(top_srcdir)/src/helper/bin2char.sh
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DEBUG_HANDLER = $(srcdir)/xscale/debug_handler.bin
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EXTRA_DIST = \
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startup.tcl \
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$(wildcard $(srcdir)/xscale/*)
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DEBUG_HEADER = xscale_debug.inc
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BUILT_SOURCES = $(DEBUG_HEADER)
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CLEANFILES = $(DEBUG_HEADER)
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$(DEBUG_HEADER): $(DEBUG_HANDLER) $(BIN2C)
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$(BIN2C) < $< > $@ || { rm -f $@; false; }
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METASOURCES = AUTO
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noinst_LTLIBRARIES = libtarget.la
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@@ -73,7 +73,7 @@ static int xscale_read_trace(struct target *);
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* mini-ICache, which is 2K of code writable only via JTAG.
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*/
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static const uint8_t xscale_debug_handler[] = {
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#include "xscale_debug.inc"
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#include "../../contrib/loaders/debug/xscale/debug_handler.inc"
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};
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static const char *const xscale_reg_list[] = {
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@@ -1,7 +0,0 @@
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arm-none-eabi-gcc -c debug_handler.S -o debug_handler.o
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arm-none-eabi-ld -EL -n -Tdebug_handler.cmd debug_handler.o -o debug_handler.out
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arm-none-eabi-objcopy -O binary debug_handler.out debug_handler.bin
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#arm-none-eabi-gcc -mbig-endian -c debug_handler.S -o debug_handler_be.o
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#arm-none-eabi-ld -EB -n -Tdebug_handler.cmd debug_handler_be.o -o debug_handler_be.out
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#arm-none-eabi-objcopy -O binary debug_handler_be.out debug_handler_be.bin
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@@ -1,716 +0,0 @@
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/***************************************************************************
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* Copyright (C) 2006 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program. If not, see <http://www.gnu.org/licenses/>. *
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***************************************************************************/
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#include "protocol.h"
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.text
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.align 4
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@ Disable thumb mode
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.code 32
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@ send word to debugger
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.macro m_send_to_debugger reg
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1:
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mrc p14, 0, r15, c14, c0, 0
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bvs 1b
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mcr p14, 0, \reg, c8, c0, 0
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.endm
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@ receive word from debugger
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.macro m_receive_from_debugger reg
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1:
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mrc p14, 0, r15, c14, c0, 0
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bpl 1b
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mrc p14, 0, \reg, c9, c0, 0
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.endm
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@ save register on debugger, small
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.macro m_small_save_reg reg
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mov r0, \reg
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bl send_to_debugger
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.endm
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@ save status register on debugger, small
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.macro m_small_save_psr
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mrs r0, spsr
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bl send_to_debugger
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.endm
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@ wait for all outstanding coprocessor accesses to complete
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.macro m_cpwait
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mrc p15, 0, r0, c2, c0, 0
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mov r0, r0
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sub pc, pc, #4
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.endm
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.global reset_handler
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.global undef_handler
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.global swi_handler
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.global prefetch_abort_handler
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.global data_abort_handler
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.global irq_handler
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.global fiq_handler
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.section .part1 , "ax"
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reset_handler:
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@ read DCSR
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mrc p14, 0, r13, c10, c0
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@ check if global enable bit (GE) is set
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ands r13, r13, #0x80000000
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bne debug_handler
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@ set global enable bit (GE)
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mov r13, #0xc0000000
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mcr p14, 0, r13, c10, c0
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debug_handler:
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@ save r0 without modifying other registers
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m_send_to_debugger r0
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@ save lr (program PC) without branching (use macro)
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m_send_to_debugger r14
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@ save non-banked registers and spsr (program CPSR)
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m_small_save_reg r1
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m_small_save_reg r2
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m_small_save_reg r3
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m_small_save_reg r4
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m_small_save_reg r5
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m_small_save_reg r6
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m_small_save_reg r7
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m_small_save_psr
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mrs r0, spsr
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@ prepare program PSR for debug use (clear Thumb, set I/F to disable interrupts)
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bic r0, r0, #PSR_T
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orr r0, r0, #(PSR_I | PSR_F)
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@ examine mode bits
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and r1, r0, #MODE_MASK
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cmp r1, #MODE_USR
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bne not_user_mode
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@ replace USR mode with SYS
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bic r0, r0, #MODE_MASK
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orr r0, r0, #MODE_SYS
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not_user_mode:
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b save_banked_registers
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@ command loop
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@ wait for command from debugger, than execute desired function
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get_command:
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bl receive_from_debugger
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@ 0x0n - register access
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cmp r0, #0x0
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beq get_banked_registers
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cmp r0, #0x1
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beq set_banked_registers
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@ 0x1n - read memory
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cmp r0, #0x11
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beq read_byte
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cmp r0, #0x12
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beq read_half_word
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cmp r0, #0x14
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beq read_word
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@ 0x2n - write memory
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cmp r0, #0x21
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beq write_byte
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cmp r0, #0x22
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beq write_half_word
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cmp r0, #0x24
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beq write_word
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@ 0x3n - program execution
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cmp r0, #0x30
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beq resume
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cmp r0, #0x31
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beq resume_w_trace
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@ 0x4n - coprocessor access
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cmp r0, #0x40
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beq read_cp_reg
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cmp r0, #0x41
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beq write_cp_reg
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@ 0x5n - cache and mmu functions
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cmp r0, #0x50
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beq clean_d_cache
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cmp r0, #0x51
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beq invalidate_d_cache
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cmp r0, #0x52
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beq invalidate_i_cache
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cmp r0, #0x53
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beq cpwait
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@ 0x6n - misc functions
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cmp r0, #0x60
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beq clear_sa
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cmp r0, #0x61
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beq read_trace_buffer
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cmp r0, #0x62
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beq clean_trace_buffer
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@ return (back to get_command)
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b get_command
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@ ----
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@ resume program execution
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resume:
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@ restore CPSR (SPSR_dbg)
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bl receive_from_debugger
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msr spsr, r0
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@ restore registers (r7 - r0)
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bl receive_from_debugger @ r7
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mov r7, r0
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bl receive_from_debugger @ r6
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mov r6, r0
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bl receive_from_debugger @ r5
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mov r5, r0
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bl receive_from_debugger @ r4
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mov r4, r0
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bl receive_from_debugger @ r3
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mov r3, r0
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bl receive_from_debugger @ r2
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mov r2, r0
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bl receive_from_debugger @ r1
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mov r1, r0
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bl receive_from_debugger @ r0
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@ resume addresss
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m_receive_from_debugger lr
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@ branch back to application code, restoring CPSR
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subs pc, lr, #0
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@ get banked registers
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@ receive mode bits from host, then run into save_banked_registers to
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get_banked_registers:
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bl receive_from_debugger
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@ save banked registers
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@ r0[4:0]: desired mode bits
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save_banked_registers:
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@ backup CPSR
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mrs r7, cpsr
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msr cpsr_c, r0
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nop
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@ keep current mode bits in r1 for later use
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and r1, r0, #MODE_MASK
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@ backup banked registers
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m_send_to_debugger r8
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m_send_to_debugger r9
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m_send_to_debugger r10
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m_send_to_debugger r11
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m_send_to_debugger r12
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m_send_to_debugger r13
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m_send_to_debugger r14
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@ if not in SYS mode (or USR, which we replaced with SYS before)
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cmp r1, #MODE_SYS
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beq no_spsr_to_save
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@ backup SPSR
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mrs r0, spsr
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m_send_to_debugger r0
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no_spsr_to_save:
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@ restore CPSR for SDS
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msr cpsr_c, r7
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nop
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@ return
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b get_command
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@ ----
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@ set banked registers
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@ receive mode bits from host, then run into save_banked_registers to
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set_banked_registers:
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bl receive_from_debugger
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@ restore banked registers
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@ r0[4:0]: desired mode bits
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restore_banked_registers:
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@ backup CPSR
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mrs r7, cpsr
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msr cpsr_c, r0
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nop
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@ keep current mode bits in r1 for later use
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and r1, r0, #MODE_MASK
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@ set banked registers
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m_receive_from_debugger r8
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m_receive_from_debugger r9
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m_receive_from_debugger r10
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m_receive_from_debugger r11
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m_receive_from_debugger r12
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m_receive_from_debugger r13
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m_receive_from_debugger r14
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@ if not in SYS mode (or USR, which we replaced with SYS before)
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cmp r1, #MODE_SYS
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beq no_spsr_to_restore
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@ set SPSR
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m_receive_from_debugger r0
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msr spsr, r0
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no_spsr_to_restore:
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@ restore CPSR for SDS
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msr cpsr_c, r7
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nop
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@ return
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b get_command
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@ ----
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read_byte:
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@ r2: address
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bl receive_from_debugger
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mov r2, r0
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@ r1: count
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bl receive_from_debugger
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mov r1, r0
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rb_loop:
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ldrb r0, [r2], #1
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@ drain write- (and fill-) buffer to work around XScale errata
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mcr p15, 0, r8, c7, c10, 4
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bl send_to_debugger
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subs r1, r1, #1
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bne rb_loop
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@ return
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b get_command
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@ ----
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read_half_word:
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@ r2: address
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bl receive_from_debugger
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mov r2, r0
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@ r1: count
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bl receive_from_debugger
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mov r1, r0
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rh_loop:
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ldrh r0, [r2], #2
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@ drain write- (and fill-) buffer to work around XScale errata
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mcr p15, 0, r8, c7, c10, 4
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bl send_to_debugger
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subs r1, r1, #1
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bne rh_loop
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@ return
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b get_command
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@ ----
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read_word:
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@ r2: address
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bl receive_from_debugger
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mov r2, r0
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@ r1: count
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bl receive_from_debugger
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mov r1, r0
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rw_loop:
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ldr r0, [r2], #4
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@ drain write- (and fill-) buffer to work around XScale errata
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mcr p15, 0, r8, c7, c10, 4
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bl send_to_debugger
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subs r1, r1, #1
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bne rw_loop
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@ return
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b get_command
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@ ----
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write_byte:
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@ r2: address
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bl receive_from_debugger
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mov r2, r0
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@ r1: count
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bl receive_from_debugger
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mov r1, r0
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wb_loop:
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bl receive_from_debugger
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strb r0, [r2], #1
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@ drain write- (and fill-) buffer to work around XScale errata
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mcr p15, 0, r8, c7, c10, 4
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subs r1, r1, #1
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bne wb_loop
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@ return
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b get_command
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@ ----
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write_half_word:
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@ r2: address
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bl receive_from_debugger
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mov r2, r0
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@ r1: count
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bl receive_from_debugger
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mov r1, r0
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wh_loop:
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bl receive_from_debugger
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strh r0, [r2], #2
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@ drain write- (and fill-) buffer to work around XScale errata
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mcr p15, 0, r8, c7, c10, 4
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subs r1, r1, #1
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bne wh_loop
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@ return
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b get_command
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@ ----
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write_word:
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@ r2: address
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bl receive_from_debugger
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mov r2, r0
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@ r1: count
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bl receive_from_debugger
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mov r1, r0
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ww_loop:
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bl receive_from_debugger
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str r0, [r2], #4
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@ drain write- (and fill-) buffer to work around XScale errata
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mcr p15, 0, r8, c7, c10, 4
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subs r1, r1, #1
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bne ww_loop
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@ return
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b get_command
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@ ----
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clear_sa:
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@ read DCSR
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mrc p14, 0, r0, c10, c0
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@ clear SA bit
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bic r0, r0, #0x20
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@ write DCSR
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mcr p14, 0, r0, c10, c0
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@ return
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b get_command
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@ ----
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clean_d_cache:
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@ r0: cache clean area
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bl receive_from_debugger
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mov r1, #1024
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clean_loop:
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mcr p15, 0, r0, c7, c2, 5
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add r0, r0, #32
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subs r1, r1, #1
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bne clean_loop
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@ return
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b get_command
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@ ----
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invalidate_d_cache:
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mcr p15, 0, r0, c7, c6, 0
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@ return
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b get_command
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@ ----
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invalidate_i_cache:
|
||||
mcr p15, 0, r0, c7, c5, 0
|
||||
|
||||
@ return
|
||||
b get_command
|
||||
|
||||
@ ----
|
||||
|
||||
cpwait:
|
||||
m_cpwait
|
||||
|
||||
@return
|
||||
b get_command
|
||||
|
||||
@ ----
|
||||
|
||||
.section .part2 , "ax"
|
||||
|
||||
read_cp_reg:
|
||||
@ requested cp register
|
||||
bl receive_from_debugger
|
||||
|
||||
adr r1, read_cp_table
|
||||
add pc, r1, r0, lsl #3
|
||||
|
||||
read_cp_table:
|
||||
mrc p15, 0, r0, c0, c0, 0 @ XSCALE_MAINID
|
||||
b read_cp_reg_reply
|
||||
mrc p15, 0, r0, c0, c0, 1 @ XSCALE_CACHETYPE
|
||||
b read_cp_reg_reply
|
||||
mrc p15, 0, r0, c1, c0, 0 @ XSCALE_CTRL
|
||||
b read_cp_reg_reply
|
||||
mrc p15, 0, r0, c1, c0, 1 @ XSCALE_AUXCTRL
|
||||
b read_cp_reg_reply
|
||||
mrc p15, 0, r0, c2, c0, 0 @ XSCALE_TTB
|
||||
b read_cp_reg_reply
|
||||
mrc p15, 0, r0, c3, c0, 0 @ XSCALE_DAC
|
||||
b read_cp_reg_reply
|
||||
mrc p15, 0, r0, c5, c0, 0 @ XSCALE_FSR
|
||||
b read_cp_reg_reply
|
||||
mrc p15, 0, r0, c6, c0, 0 @ XSCALE_FAR
|
||||
b read_cp_reg_reply
|
||||
mrc p15, 0, r0, c13, c0, 0 @ XSCALE_PID
|
||||
b read_cp_reg_reply
|
||||
mrc p15, 0, r0, c15, c0, 0 @ XSCALE_CP_ACCESS
|
||||
b read_cp_reg_reply
|
||||
mrc p15, 0, r0, c14, c8, 0 @ XSCALE_IBCR0
|
||||
b read_cp_reg_reply
|
||||
mrc p15, 0, r0, c14, c9, 0 @ XSCALE_IBCR1
|
||||
b read_cp_reg_reply
|
||||
mrc p15, 0, r0, c14, c0, 0 @ XSCALE_DBR0
|
||||
b read_cp_reg_reply
|
||||
mrc p15, 0, r0, c14, c3, 0 @ XSCALE_DBR1
|
||||
b read_cp_reg_reply
|
||||
mrc p15, 0, r0, c14, c4, 0 @ XSCALE_DBCON
|
||||
b read_cp_reg_reply
|
||||
mrc p14, 0, r0, c11, c0, 0 @ XSCALE_TBREG
|
||||
b read_cp_reg_reply
|
||||
mrc p14, 0, r0, c12, c0, 0 @ XSCALE_CHKPT0
|
||||
b read_cp_reg_reply
|
||||
mrc p14, 0, r0, c13, c0, 0 @ XSCALE_CHKPT1
|
||||
b read_cp_reg_reply
|
||||
mrc p14, 0, r0, c10, c0, 0 @ XSCALE_DCSR
|
||||
b read_cp_reg_reply
|
||||
|
||||
read_cp_reg_reply:
|
||||
bl send_to_debugger
|
||||
|
||||
@ return
|
||||
b get_command
|
||||
|
||||
@ ----
|
||||
|
||||
write_cp_reg:
|
||||
@ requested cp register
|
||||
bl receive_from_debugger
|
||||
mov r1, r0
|
||||
|
||||
@ value to be written
|
||||
bl receive_from_debugger
|
||||
|
||||
adr r2, write_cp_table
|
||||
add pc, r2, r1, lsl #3
|
||||
|
||||
write_cp_table:
|
||||
mcr p15, 0, r0, c0, c0, 0 @ XSCALE_MAINID (0x0)
|
||||
b get_command
|
||||
mcr p15, 0, r0, c0, c0, 1 @ XSCALE_CACHETYPE (0x1)
|
||||
b get_command
|
||||
mcr p15, 0, r0, c1, c0, 0 @ XSCALE_CTRL (0x2)
|
||||
b get_command
|
||||
mcr p15, 0, r0, c1, c0, 1 @ XSCALE_AUXCTRL (0x3)
|
||||
b get_command
|
||||
mcr p15, 0, r0, c2, c0, 0 @ XSCALE_TTB (0x4)
|
||||
b get_command
|
||||
mcr p15, 0, r0, c3, c0, 0 @ XSCALE_DAC (0x5)
|
||||
b get_command
|
||||
mcr p15, 0, r0, c5, c0, 0 @ XSCALE_FSR (0x6)
|
||||
b get_command
|
||||
mcr p15, 0, r0, c6, c0, 0 @ XSCALE_FAR (0x7)
|
||||
b get_command
|
||||
mcr p15, 0, r0, c13, c0, 0 @ XSCALE_PID (0x8)
|
||||
b get_command
|
||||
mcr p15, 0, r0, c15, c0, 0 @ XSCALE_CP_ACCESS (0x9)
|
||||
b get_command
|
||||
mcr p15, 0, r0, c14, c8, 0 @ XSCALE_IBCR0 (0xa)
|
||||
b get_command
|
||||
mcr p15, 0, r0, c14, c9, 0 @ XSCALE_IBCR1 (0xb)
|
||||
b get_command
|
||||
mcr p15, 0, r0, c14, c0, 0 @ XSCALE_DBR0 (0xc)
|
||||
b get_command
|
||||
mcr p15, 0, r0, c14, c3, 0 @ XSCALE_DBR1 (0xd)
|
||||
b get_command
|
||||
mcr p15, 0, r0, c14, c4, 0 @ XSCALE_DBCON (0xe)
|
||||
b get_command
|
||||
mcr p14, 0, r0, c11, c0, 0 @ XSCALE_TBREG (0xf)
|
||||
b get_command
|
||||
mcr p14, 0, r0, c12, c0, 0 @ XSCALE_CHKPT0 (0x10)
|
||||
b get_command
|
||||
mcr p14, 0, r0, c13, c0, 0 @ XSCALE_CHKPT1 (0x11)
|
||||
b get_command
|
||||
mcr p14, 0, r0, c10, c0, 0 @ XSCALE_DCSR (0x12)
|
||||
b get_command
|
||||
|
||||
@ ----
|
||||
|
||||
read_trace_buffer:
|
||||
|
||||
@ dump 256 entries from trace buffer
|
||||
mov r1, #256
|
||||
read_tb_loop:
|
||||
mrc p14, 0, r0, c11, c0, 0 @ XSCALE_TBREG
|
||||
bl send_to_debugger
|
||||
subs r1, r1, #1
|
||||
bne read_tb_loop
|
||||
|
||||
@ dump checkpoint register 0
|
||||
mrc p14, 0, r0, c12, c0, 0 @ XSCALE_CHKPT0 (0x10)
|
||||
bl send_to_debugger
|
||||
|
||||
@ dump checkpoint register 1
|
||||
mrc p14, 0, r0, c13, c0, 0 @ XSCALE_CHKPT1 (0x11)
|
||||
bl send_to_debugger
|
||||
|
||||
@ return
|
||||
b get_command
|
||||
|
||||
@ ----
|
||||
|
||||
clean_trace_buffer:
|
||||
|
||||
@ clean 256 entries from trace buffer
|
||||
mov r1, #256
|
||||
clean_tb_loop:
|
||||
mrc p14, 0, r0, c11, c0, 0 @ XSCALE_TBREG
|
||||
subs r1, r1, #1
|
||||
bne clean_tb_loop
|
||||
|
||||
@ return
|
||||
b get_command
|
||||
|
||||
@ ----
|
||||
|
||||
|
||||
@ resume program execution with trace buffer enabled
|
||||
resume_w_trace:
|
||||
@ restore CPSR (SPSR_dbg)
|
||||
bl receive_from_debugger
|
||||
msr spsr, r0
|
||||
|
||||
@ restore registers (r7 - r0)
|
||||
bl receive_from_debugger @ r7
|
||||
mov r7, r0
|
||||
bl receive_from_debugger @ r6
|
||||
mov r6, r0
|
||||
bl receive_from_debugger @ r5
|
||||
mov r5, r0
|
||||
bl receive_from_debugger @ r4
|
||||
mov r4, r0
|
||||
bl receive_from_debugger @ r3
|
||||
mov r3, r0
|
||||
bl receive_from_debugger @ r2
|
||||
mov r2, r0
|
||||
bl receive_from_debugger @ r1
|
||||
mov r1, r0
|
||||
bl receive_from_debugger @ r0
|
||||
|
||||
@ resume addresss
|
||||
m_receive_from_debugger lr
|
||||
|
||||
mrc p14, 0, r13, c10, c0, 0 @ XSCALE_DCSR
|
||||
orr r13, r13, #1
|
||||
mcr p14, 0, r13, c10, c0, 0 @ XSCALE_DCSR
|
||||
|
||||
@ branch back to application code, restoring CPSR
|
||||
subs pc, lr, #0
|
||||
|
||||
undef_handler:
|
||||
swi_handler:
|
||||
prefetch_abort_handler:
|
||||
data_abort_handler:
|
||||
irq_handler:
|
||||
fiq_handler:
|
||||
1:
|
||||
b 1b
|
||||
|
||||
send_to_debugger:
|
||||
m_send_to_debugger r0
|
||||
mov pc, lr
|
||||
|
||||
receive_from_debugger:
|
||||
m_receive_from_debugger r0
|
||||
mov pc, lr
|
||||
|
||||
Binary file not shown.
@@ -1,49 +0,0 @@
|
||||
/* identify the Entry Point */
|
||||
ENTRY(reset_handler)
|
||||
|
||||
/* specify the mini-ICache memory areas */
|
||||
MEMORY
|
||||
{
|
||||
mini_icache_0 (x) : ORIGIN = 0x0, LENGTH = 1024 /* first part of mini icache (sets 0-31) */
|
||||
mini_icache_1 (x) : ORIGIN = 0x400, LENGTH = 1024 /* second part of mini icache (sets 0-31) */
|
||||
}
|
||||
|
||||
/* now define the output sections */
|
||||
SECTIONS
|
||||
{
|
||||
.part1 :
|
||||
{
|
||||
LONG(0)
|
||||
LONG(0)
|
||||
LONG(0)
|
||||
LONG(0)
|
||||
LONG(0)
|
||||
LONG(0)
|
||||
LONG(0)
|
||||
LONG(0)
|
||||
*(.part1)
|
||||
} >mini_icache_0
|
||||
|
||||
.part2 :
|
||||
{
|
||||
LONG(0)
|
||||
LONG(0)
|
||||
LONG(0)
|
||||
LONG(0)
|
||||
LONG(0)
|
||||
LONG(0)
|
||||
LONG(0)
|
||||
LONG(0)
|
||||
*(.part2)
|
||||
FILL(0x0)
|
||||
} >mini_icache_1
|
||||
|
||||
/DISCARD/ :
|
||||
{
|
||||
*(.text)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.data)
|
||||
*(.bss)
|
||||
}
|
||||
}
|
||||
@@ -1,68 +0,0 @@
|
||||
/***************************************************************************
|
||||
* Copyright (C) 2006 by Dominic Rath *
|
||||
* Dominic.Rath@gmx.de *
|
||||
* *
|
||||
* This program is free software; you can redistribute it and/or modify *
|
||||
* it under the terms of the GNU General Public License as published by *
|
||||
* the Free Software Foundation; either version 2 of the License, or *
|
||||
* (at your option) any later version. *
|
||||
* *
|
||||
* This program is distributed in the hope that it will be useful, *
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
|
||||
* GNU General Public License for more details. *
|
||||
* *
|
||||
* You should have received a copy of the GNU General Public License *
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>. *
|
||||
***************************************************************************/
|
||||
|
||||
#define REG_R0 0
|
||||
#define REG_R1 1
|
||||
#define REG_R2 2
|
||||
#define REG_R3 3
|
||||
#define REG_R4 4
|
||||
#define REG_R5 5
|
||||
#define REG_R6 6
|
||||
#define REG_R7 7
|
||||
#define REG_R8 8
|
||||
#define REG_R9 9
|
||||
#define REG_R10 10
|
||||
#define REG_R11 11
|
||||
#define REG_R12 12
|
||||
#define REG_R13 13
|
||||
#define REG_R14 14
|
||||
#define REG_R15 15
|
||||
#define REG_CPSR 16
|
||||
#define REG_SPSR 17
|
||||
|
||||
#define MODE_USR 0x10
|
||||
#define MODE_FIQ 0x11
|
||||
#define MODE_IRQ 0x12
|
||||
#define MODE_SVC 0x13
|
||||
#define MODE_ABT 0x17
|
||||
#define MODE_UND 0x1b
|
||||
#define MODE_SYS 0x1f
|
||||
|
||||
#define MODE_ANY 0x40
|
||||
#define MODE_CURRENT 0x80
|
||||
|
||||
#define MODE_MASK 0x1f
|
||||
#define PSR_I 0x80
|
||||
#define PSR_F 0x40
|
||||
#define PSR_T 0x20
|
||||
|
||||
#define XSCALE_DBG_MAINID 0x0
|
||||
#define XSCALE_DBG_CACHETYPE 0x1
|
||||
#define XSCALE_DBG_CTRL 0x2
|
||||
#define XSCALE_DBG_AUXCTRL 0x3
|
||||
#define XSCALE_DBG_TTB 0x4
|
||||
#define XSCALE_DBG_DAC 0x5
|
||||
#define XSCALE_DBG_FSR 0x6
|
||||
#define XSCALE_DBG_FAR 0x7
|
||||
#define XSCALE_DBG_PID 0x8
|
||||
#define XSCALE_DBG_CPACCESS 0x9
|
||||
#define XSCALE_DBG_IBCR0 0xa
|
||||
#define XSCALE_DBG_IBCR1 0xb
|
||||
#define XSCALE_DBG_DBR0 0xc
|
||||
#define XSCALE_DBG_DBR1 0xd
|
||||
#define XSCALE_DBG_DBCON 0xe
|
||||
Reference in New Issue
Block a user