forked from auracaster/openocd
flash/nor: Add nRF54 NVM driver
The driver is intentionally not integrated into the 'nRF5' driver in order to serve as a kind of 'test vehicle' for non-flash memory drivers. The driver does not support the UICR but only the main memory region. Change-Id: Ia69527c4e07d40e8805186be8e988c0d74c12041 Signed-off-by: Marc Schink <dev@zapb.de>
This commit is contained in:
Marc Schink
committed by
Holger Mößinger (hm2dev)
Holger Mößinger (hm2dev)
parent
74d0cff2fe
commit
1d06d22892
@@ -53,6 +53,7 @@ NOR_DRIVERS = \
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%D%/non_cfi.c \
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%D%/npcx.c \
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%D%/nrf5.c \
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%D%/nrf54.c \
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%D%/numicro.c \
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%D%/ocl.c \
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%D%/pic32mx.c \
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@@ -283,6 +283,7 @@ extern const struct flash_driver niietcm4_flash;
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extern const struct flash_driver npcx_flash;
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extern const struct flash_driver nrf51_flash;
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extern const struct flash_driver nrf5_flash;
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extern const struct flash_driver nrf54_flash;
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extern const struct flash_driver numicro_flash;
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extern const struct flash_driver ocl_flash;
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extern const struct flash_driver pic32mx_flash;
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@@ -62,6 +62,7 @@ static const struct flash_driver * const flash_drivers[] = {
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&npcx_flash,
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&nrf51_flash,
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&nrf5_flash,
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&nrf54_flash,
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&numicro_flash,
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&ocl_flash,
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&pic32mx_flash,
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376
src/flash/nor/nrf54.c
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376
src/flash/nor/nrf54.c
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@@ -0,0 +1,376 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "imp.h"
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#include <helper/binarybuffer.h>
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#include <target/algorithm.h>
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#include <target/armv7m.h>
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#include <helper/types.h>
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#include <helper/time_support.h>
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#include <helper/bits.h>
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/*
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* Related documents
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*
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* nRF54L15, nRF54L10, and nRF54L05 Wireless SoCs
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* https://docs-be.nordicsemi.com/bundle/ps_nrf54L15/page/pdf/nRF54L15_nRF54L10_nRF54L05_Datasheet_v0.8.pdf
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*
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* nRF54L Series Production Programming
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* https://docs-be.nordicsemi.com/bundle/nan_047/attach/nan_047.pdf
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*/
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#define NRF54_FICR_BASE_ADDR 0x00FFC000
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#define NRF54_FICR_INFO_PART_REG 0x31c
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#define NRF54_FICR_INFO_VARIANT_REG 0x320
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#define NRF54_FICR_INFO_PACKAGE_REG 0x324
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#define NRF54_FICR_INFO_RAM_REG 0x328
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#define NRF54_FICR_INFO_RRAM_REG 0x32C
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#define NRF54_RRAM_BASE_ADDR 0x00000000
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#define NRF54_RRAMC_BASE_ADDR 0x5004B000
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#define NRF54_RRAMC_REG_CONFIG 0x500
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#define NRF54_RRAMC_REG_READY 0x400
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#define NRF54_RRAMC_CONFIG_WEN BIT(0)
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struct {
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uint32_t id;
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const char *name;
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} nrf54_part_names[] = {
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{ 0x00054B15, "nRF54L15" },
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{ 0x00054B10, "nRF54L10" },
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{ 0x00054B05, "nRF54L05" },
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};
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struct nrf54_ficr_info {
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// Part identification number.
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uint32_t part;
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/*
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* Part variant (V), hardware version (H) and production
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* configuration (P) encoded as ASCII: <VV><H><P>.
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*/
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uint32_t variant;
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/*
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* Package variant (P) encoded as ASCII: <__><PP>, where (_) indicates
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* the null character.
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*/
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uint32_t package;
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// SRAM size in KiB.
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uint32_t sram_size;
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// RRAM size in KiB.
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uint32_t rram_size;
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};
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struct nrf54_info {
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bool probed;
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const char *part_name;
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struct nrf54_ficr_info ficr_info;
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};
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static int nrf54_read_ficr_info(struct target *target,
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struct nrf54_ficr_info *info)
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{
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int retval = target_read_u32(target,
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NRF54_FICR_BASE_ADDR + NRF54_FICR_INFO_PART_REG, &info->part);
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if (retval != ERROR_OK)
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return retval;
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retval = target_read_u32(target,
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NRF54_FICR_BASE_ADDR + NRF54_FICR_INFO_VARIANT_REG, &info->variant);
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if (retval != ERROR_OK)
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return retval;
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retval = target_read_u32(target,
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NRF54_FICR_BASE_ADDR + NRF54_FICR_INFO_PACKAGE_REG, &info->package);
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if (retval != ERROR_OK)
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return retval;
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retval = target_read_u32(target,
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NRF54_FICR_BASE_ADDR + NRF54_FICR_INFO_RAM_REG, &info->sram_size);
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if (retval != ERROR_OK)
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return retval;
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retval = target_read_u32(target,
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NRF54_FICR_BASE_ADDR + NRF54_FICR_INFO_RRAM_REG, &info->rram_size);
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if (retval != ERROR_OK)
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return retval;
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return ERROR_OK;
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}
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static const char *nrf54_get_part_name(uint32_t id)
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{
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for (size_t i = 0; i < ARRAY_SIZE(nrf54_part_names); i++) {
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if (id == nrf54_part_names[i].id)
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return nrf54_part_names[i].name;
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}
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return NULL;
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}
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static void nrf54_u32_to_str(uint32_t data, char *str)
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{
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uint8_t tmp[4];
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h_u32_to_be(tmp, data);
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memcpy(str, tmp, 4);
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str[4] = '\0';
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}
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static bool nrf54_get_chip_type_str(const struct nrf54_info *info,
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char *buf, size_t size)
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{
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char variant[5];
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nrf54_u32_to_str(info->ficr_info.variant, variant);
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char package[5];
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// Note that the first two characters are always null characters.
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nrf54_u32_to_str(info->ficr_info.package, package);
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int res = snprintf(buf, size, "%s-%c%c%c%c",
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info->part_name, package[2], package[3], variant[0], variant[1]);
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if (res < 0)
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return false;
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if ((size_t)res >= size)
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return false;
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return true;
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}
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static int nrf54_info(struct flash_bank *bank, struct command_invocation *cmd)
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{
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struct nrf54_info *info = bank->driver_priv;
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char chip_type[128];
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if (!nrf54_get_chip_type_str(info, chip_type, sizeof(chip_type))) {
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LOG_ERROR("Failed to build chip type string");
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return ERROR_FAIL;
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}
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command_print_sameline(cmd, "%s %" PRIu32 " KiB RRAM, %" PRIu32 " KiB SRAM",
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chip_type, info->ficr_info.rram_size, info->ficr_info.sram_size);
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return ERROR_OK;
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}
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static int nrf54_probe(struct flash_bank *bank)
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{
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struct target *target = bank->target;
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struct nrf54_info *nrf54_info = bank->driver_priv;
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struct nrf54_ficr_info *ficr_info = &nrf54_info->ficr_info;
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int retval = nrf54_read_ficr_info(target, ficr_info);
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if (retval != ERROR_OK) {
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LOG_ERROR("Failed to load FICR from device");
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return retval;
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}
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const char *part_name = nrf54_get_part_name(ficr_info->part);
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if (!part_name) {
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LOG_ERROR("Unknown device with part number 0x%08" PRIx32,
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nrf54_info->ficr_info.part);
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return ERROR_FAIL;
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}
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nrf54_info->part_name = part_name;
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bank->size = ficr_info->rram_size * 1024;
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nrf54_info->probed = true;
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// RRAM has no alignment constraints, see section 4.2.6.2 in the datasheet.
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bank->write_start_alignment = 0;
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bank->write_end_alignment = 0;
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return ERROR_OK;
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}
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static int nrf54_auto_probe(struct flash_bank *bank)
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{
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struct nrf54_info *info = bank->driver_priv;
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if (!info->probed)
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return nrf54_probe(bank);
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return ERROR_OK;
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}
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static int nrf54_wait_until_ready(struct target *target, uint32_t timeout)
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{
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const int64_t start_time = timeval_ms();
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while (true) {
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uint32_t ready;
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int retval = target_read_u32(target,
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NRF54_RRAMC_BASE_ADDR + NRF54_RRAMC_REG_READY, &ready);
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if (retval != ERROR_OK)
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return retval;
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/*
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* Send a 'keep-alive' signal before checking if the target is ready.
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* The target is usually ready immediately, so without this 'keep-alive'
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* it would process consecutive write calls without any keep-alive and
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* eventually trigger a timeout.
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*/
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keep_alive();
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if (ready)
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break;
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if ((timeval_ms() - start_time) > timeout) {
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LOG_ERROR("Timed out waiting for RRAM");
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return ERROR_FAIL;
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}
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}
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return ERROR_OK;
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}
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static int nrf54_write(struct flash_bank *bank, const uint8_t *buffer,
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uint32_t offset, uint32_t count)
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{
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struct target *target = bank->target;
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if (target->state != TARGET_HALTED) {
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LOG_ERROR("Target not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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// Write buffer size in 128-bit words, we always use the maximum.
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const uint32_t write_buffer_size = 32;
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// Unlock RRAM to enables writes and configure the write buffer size.
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int retval = target_write_u32(target,
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NRF54_RRAMC_BASE_ADDR + NRF54_RRAMC_REG_CONFIG,
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(write_buffer_size << 8) | NRF54_RRAMC_CONFIG_WEN);
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if (retval != ERROR_OK) {
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LOG_ERROR("Failed to unlock RRAM");
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return retval;
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}
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retval = nrf54_wait_until_ready(target, 1000);
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if (retval != ERROR_OK)
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goto error;
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// See section (4.2.6.2) in the datasheet about writing to RRAM.
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const uint32_t buffer_size = (write_buffer_size == 0) ?
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4 : write_buffer_size * 16;
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while (count > 0) {
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const uint32_t write_size = MIN(buffer_size, count);
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retval = target_write_buffer(target, bank->base + offset, write_size,
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buffer);
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if (retval != ERROR_OK)
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goto error;
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retval = nrf54_wait_until_ready(target, 1000);
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if (retval != ERROR_OK)
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goto error;
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offset += write_size;
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buffer += write_size;
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count -= write_size;
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}
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// Check if there is data in the write-buffer that needs to be committed.
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uint32_t buf_status;
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retval = target_read_u32(target, NRF54_RRAMC_BASE_ADDR + 0x418, &buf_status);
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if (retval != ERROR_OK) {
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LOG_ERROR("Failed to read write-buffer status");
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goto error;
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}
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if (!buf_status) {
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LOG_DEBUG("Commit data from write-buffer to RRAM");
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retval = target_write_u32(target, NRF54_RRAMC_BASE_ADDR + 0x8, 0x1);
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if (retval != ERROR_OK) {
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LOG_ERROR("Failed to start write-buffer commit task");
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goto error;
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}
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retval = nrf54_wait_until_ready(target, 1000);
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if (retval != ERROR_OK) {
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LOG_ERROR("Timed out during write-buffer commit task");
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goto error;
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}
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}
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int retval_lock;
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error:
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// Lock RRAMC and disable writes.
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retval_lock = target_write_u32(target,
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NRF54_RRAMC_BASE_ADDR + NRF54_RRAMC_REG_CONFIG, 0x0);
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if (retval != ERROR_OK)
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return retval;
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if (retval_lock != ERROR_OK) {
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LOG_ERROR("Failed to lock RRAMC");
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return retval_lock;
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}
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return ERROR_OK;
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}
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static int nrf54_erase(struct flash_bank *bank, unsigned int first,
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unsigned int last)
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{
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return ERROR_FLASH_OPER_UNSUPPORTED;
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}
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FLASH_BANK_COMMAND_HANDLER(nrf54_flash_bank_command)
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{
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if (bank->base != NRF54_RRAM_BASE_ADDR) {
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LOG_ERROR("Bank base address must be %" PRIx32, NRF54_RRAM_BASE_ADDR);
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return ERROR_FAIL;
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}
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struct nrf54_info *nrf54_info = calloc(1, sizeof(struct nrf54_info));
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if (!nrf54_info) {
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LOG_ERROR("Failed to allocate memory");
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return ERROR_FAIL;
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}
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nrf54_info->probed = false;
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bank->driver_priv = nrf54_info;
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return ERROR_OK;
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}
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static const struct command_registration nrf54_command_handlers[] = {
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{
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.name = "nrf54",
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.mode = COMMAND_ANY,
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.help = "nrf54 flash command group",
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.usage = "",
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},
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COMMAND_REGISTRATION_DONE
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};
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const struct flash_driver nrf54_flash = {
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.name = "nrf54",
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.commands = nrf54_command_handlers,
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.flash_bank_command = nrf54_flash_bank_command,
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.info = nrf54_info,
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.erase = nrf54_erase,
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.write = nrf54_write,
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.read = default_flash_read,
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.probe = nrf54_probe,
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.auto_probe = nrf54_auto_probe,
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.erase_check = default_flash_blank_check,
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.free_driver_priv = default_flash_free_driver_priv,
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};
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Reference in New Issue
Block a user