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cortex_a: Use endianness for soft breakpoints

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Fix endianness for cortex_r4 and cortex_r5 when inserting software
breakpoints. Because the cortex_a target is used by the cortex_r
architecture and some chips start in BE by default (e.g. TMS570)

Change-Id: I68b7fe7c4604de67fee2e64fff0fad2691659a58
Signed-off-by: Lucien Dufour <lucien.buchmann@dufour.aero>
Reviewed-on: https://review.openocd.org/c/openocd/+/8909
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
This commit is contained in:
Lucien Dufour
2025-05-15 14:31:25 +02:00
committed by Antonio Borneo
parent c545b9c4ab
commit 25b99ae456
2 changed files with 16 additions and 0 deletions
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13
src/target/cortex_a.c
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@@ -1380,6 +1380,19 @@ static int cortex_a_set_breakpoint(struct target *target,
buf_set_u32(code, 0, 32, ARMV5_BKPT(0x11));
}
/*
* ARMv7-A/R fetches instructions in little-endian on both LE and BE CPUs.
* But Cortex-R4 and Cortex-R5 big-endian require BE instructions.
* https://developer.arm.com/documentation/den0042/a/Coding-for-Cortex-R-Processors/Endianness
* https://developer.arm.com/documentation/den0013/d/Porting/Endianness
*/
if ((((cortex_a->cpuid & CPUDBG_CPUID_MASK) == CPUDBG_CPUID_CORTEX_R4) ||
((cortex_a->cpuid & CPUDBG_CPUID_MASK) == CPUDBG_CPUID_CORTEX_R5)) &&
target->endianness == TARGET_BIG_ENDIAN) {
// In place swapping is allowed
buf_bswap32(code, code, 4);
}
retval = target_read_memory(target,
breakpoint->address & 0xFFFFFFFE,
breakpoint->length, 1,