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arm_adi_v5: Adding Nuvoton NPCX quirk

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We found that the NPCX has an issue with the byte lanes so that non byte
aligned writes aren't working. To overcome this, for byte accesses we
copy the byte to be written to all of the byte lanes.

doc: Document command nu_npcx_quirks

Signed-off-by: benjbender <benjbender@gmail.com>
[Andreas Fritiofson: Squashed commits]
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Change-Id: I9ef63bf692f4e68f57459e1ec33f3abcbf533cd2
Reviewed-on: https://review.openocd.org/c/openocd/+/6630
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Ben Bender
2021-10-05 10:58:57 +03:00
committed by Antonio Borneo
parent f97915f248
commit 2c6571b9b1
3 changed files with 42 additions and 0 deletions
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4
src/target/arm_adi_v5.h
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@@ -359,6 +359,10 @@ struct adiv5_dap {
* swizzle appropriately. */
bool ti_be_32_quirks;
/* The Nuvoton NPCX M4 has an issue with writing to non-4-byte-aligned mmios.
* The work around is to repeat the data in all 4 bytes of DRW */
bool nu_npcx_quirks;
/**
* STLINK adapter need to know if last AP operation was read or write, and
* in case of write has to flush it with a dummy read from DP_RDBUFF