From 3483756cba5038335654bee437b5f17b7e6b88fd Mon Sep 17 00:00:00 2001 From: Tomas Vanek Date: Thu, 15 May 2025 14:58:07 +0800 Subject: [PATCH] target/riscv: check nextdm address in abits range Imported from https://github.com/riscv-collab/riscv-openocd/pull/1257 developed by Mark Zhuang When abits not correctly configured, we hope to detect it as soon as possible. Change-Id: I0b7b170c39761fb531dda0747f88ace3f39ae03b Signed-off-by: Tomas Vanek Reviewed-on: https://review.openocd.org/c/openocd/+/9141 Reviewed-by: Evgeniy Naydanov Tested-by: jenkins --- src/target/riscv/riscv-013.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index d2afdba2d..3308f40b9 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -538,6 +538,7 @@ static bool check_dbgbase_exists(struct target *target) { uint32_t next_dm = 0; unsigned int count = 1; + riscv013_info_t *info = get_info(target); LOG_TARGET_DEBUG(target, "Searching for DM with DMI base address (dbgbase) = 0x%x", target->dbgbase); while (1) { @@ -552,6 +553,12 @@ static bool check_dbgbase_exists(struct target *target) LOG_TARGET_ERROR(target, "Reached the end of DM chain (detected %u DMs in total).", count); break; } + if (next_dm >> info->abits) { + LOG_TARGET_ERROR(target, "The address of the next Debug Module does not fit into %u bits, " + "which is the width of the DMI bus address. This is a HW bug", + info->abits); + break; + } /* Safety: Avoid looping forever in case of buggy nextdm values in the hardware. */ if (count++ > RISCV_MAX_DMS) { LOG_TARGET_ERROR(target, "Supporting no more than %d DMs on a DMI bus. Aborting", RISCV_MAX_DMS);