From 36a2b6c6f861e194899979e71b02c40eb9d8182e Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Sat, 28 Jun 2025 11:21:26 +0200 Subject: [PATCH] flash: nor: align switch and case statements The coding style requires the 'case' to be at the same indentation level of its 'switch' statement. Align the code accordingly. No changes are reported by git log -p -w --ignore-blank-lines --patience Change-Id: I6be44efd5189b671caabcf6753bb82ef44521440 Signed-off-by: Antonio Borneo Reviewed-on: https://review.openocd.org/c/openocd/+/9034 Tested-by: jenkins --- src/flash/nor/ambiqmicro.c | 55 ++- src/flash/nor/at91sam3.c | 335 +++++++------ src/flash/nor/at91sam4.c | 351 +++++++------- src/flash/nor/at91sam4l.c | 26 +- src/flash/nor/at91sam7.c | 296 ++++++------ src/flash/nor/atsamv.c | 84 ++-- src/flash/nor/cc26xx.c | 142 +++--- src/flash/nor/cfi.c | 374 +++++++-------- src/flash/nor/efm32.c | 56 +-- src/flash/nor/em357.c | 60 +-- src/flash/nor/kinetis.c | 36 +- src/flash/nor/kinetis_ke.c | 217 ++++----- src/flash/nor/lpc2000.c | 958 ++++++++++++++++++------------------- src/flash/nor/msp432.c | 262 +++++----- src/flash/nor/ocl.c | 30 +- src/flash/nor/psoc6.c | 42 +- src/flash/nor/stellaris.c | 96 ++-- src/flash/nor/stmqspi.c | 32 +- src/flash/nor/stmsmi.c | 30 +- src/flash/nor/str7x.c | 30 +- src/flash/nor/str9x.c | 60 +-- src/flash/nor/str9xpec.c | 44 +- src/flash/nor/tcl.c | 112 ++--- src/flash/nor/tms470.c | 174 +++---- src/flash/nor/xcf.c | 40 +- 25 files changed, 1967 insertions(+), 1975 deletions(-) diff --git a/src/flash/nor/ambiqmicro.c b/src/flash/nor/ambiqmicro.c index 67cc6b68a..cb9fa5ed7 100644 --- a/src/flash/nor/ambiqmicro.c +++ b/src/flash/nor/ambiqmicro.c @@ -190,37 +190,36 @@ static int ambiqmicro_read_part_info(struct flash_bank *bank) ambiqmicro_info->target_class = (part_num & 0xFF000000) >> 24; switch (ambiqmicro_info->target_class) { - case 1: /* 1 - Apollo */ - case 5: /* 5 - Apollo Bootloader */ - bank->base = bank->bank_number * 0x40000; - ambiqmicro_info->pagesize = 2048; - ambiqmicro_info->flshsiz = + case 1: /* 1 - Apollo */ + case 5: /* 5 - Apollo Bootloader */ + bank->base = bank->bank_number * 0x40000; + ambiqmicro_info->pagesize = 2048; + ambiqmicro_info->flshsiz = apollo_flash_size[(part_num & 0x00F00000) >> 20]; - ambiqmicro_info->sramsiz = + ambiqmicro_info->sramsiz = apollo_sram_size[(part_num & 0x000F0000) >> 16]; - ambiqmicro_info->num_pages = ambiqmicro_info->flshsiz / + ambiqmicro_info->num_pages = ambiqmicro_info->flshsiz / + ambiqmicro_info->pagesize; + if (ambiqmicro_info->num_pages > 128) { + ambiqmicro_info->num_pages = 128; + ambiqmicro_info->flshsiz = 1024 * 256; + } + break; + + default: + LOG_INFO("Unknown Class. Using Apollo-64 as default."); + + bank->base = bank->bank_number * 0x40000; + ambiqmicro_info->pagesize = 2048; + ambiqmicro_info->flshsiz = apollo_flash_size[1]; + ambiqmicro_info->sramsiz = apollo_sram_size[0]; + ambiqmicro_info->num_pages = ambiqmicro_info->flshsiz / ambiqmicro_info->pagesize; - if (ambiqmicro_info->num_pages > 128) { - ambiqmicro_info->num_pages = 128; - ambiqmicro_info->flshsiz = 1024 * 256; - } - break; - - default: - LOG_INFO("Unknown Class. Using Apollo-64 as default."); - - bank->base = bank->bank_number * 0x40000; - ambiqmicro_info->pagesize = 2048; - ambiqmicro_info->flshsiz = apollo_flash_size[1]; - ambiqmicro_info->sramsiz = apollo_sram_size[0]; - ambiqmicro_info->num_pages = ambiqmicro_info->flshsiz / - ambiqmicro_info->pagesize; - if (ambiqmicro_info->num_pages > 128) { - ambiqmicro_info->num_pages = 128; - ambiqmicro_info->flshsiz = 1024 * 256; - } - break; - + if (ambiqmicro_info->num_pages > 128) { + ambiqmicro_info->num_pages = 128; + ambiqmicro_info->flshsiz = 1024 * 256; + } + break; } if (ambiqmicro_info->target_class < ARRAY_SIZE(ambiqmicro_parts)) diff --git a/src/flash/nor/at91sam3.c b/src/flash/nor/at91sam3.c index 4042d32de..5f551681d 100644 --- a/src/flash/nor/at91sam3.c +++ b/src/flash/nor/at91sam3.c @@ -2040,40 +2040,39 @@ do_retry: /* Check command & argument */ switch (command) { + case AT91C_EFC_FCMD_WP: + case AT91C_EFC_FCMD_WPL: + case AT91C_EFC_FCMD_EWP: + case AT91C_EFC_FCMD_EWPL: + /* case AT91C_EFC_FCMD_EPL: */ + /* case AT91C_EFC_FCMD_EPA: */ + case AT91C_EFC_FCMD_SLB: + case AT91C_EFC_FCMD_CLB: + n = (private->size_bytes / private->page_size); + if (argument >= n) + LOG_ERROR("*BUG*: Embedded flash has only %" PRIu32 " pages", n); + break; - case AT91C_EFC_FCMD_WP: - case AT91C_EFC_FCMD_WPL: - case AT91C_EFC_FCMD_EWP: - case AT91C_EFC_FCMD_EWPL: - /* case AT91C_EFC_FCMD_EPL: */ - /* case AT91C_EFC_FCMD_EPA: */ - case AT91C_EFC_FCMD_SLB: - case AT91C_EFC_FCMD_CLB: - n = (private->size_bytes / private->page_size); - if (argument >= n) - LOG_ERROR("*BUG*: Embedded flash has only %" PRIu32 " pages", n); - break; + case AT91C_EFC_FCMD_SFB: + case AT91C_EFC_FCMD_CFB: + if (argument >= private->chip->details.n_gpnvms) { + LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs", + private->chip->details.n_gpnvms); + } + break; - case AT91C_EFC_FCMD_SFB: - case AT91C_EFC_FCMD_CFB: - if (argument >= private->chip->details.n_gpnvms) { - LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs", - private->chip->details.n_gpnvms); - } - break; - - case AT91C_EFC_FCMD_GETD: - case AT91C_EFC_FCMD_EA: - case AT91C_EFC_FCMD_GLB: - case AT91C_EFC_FCMD_GFB: - case AT91C_EFC_FCMD_STUI: - case AT91C_EFC_FCMD_SPUI: - if (argument != 0) - LOG_ERROR("Argument is meaningless for cmd: %d", command); - break; - default: - LOG_ERROR("Unknown command %d", command); - break; + case AT91C_EFC_FCMD_GETD: + case AT91C_EFC_FCMD_EA: + case AT91C_EFC_FCMD_GLB: + case AT91C_EFC_FCMD_GFB: + case AT91C_EFC_FCMD_STUI: + case AT91C_EFC_FCMD_SPUI: + if (argument != 0) + LOG_ERROR("Argument is meaningless for cmd: %d", command); + break; + default: + LOG_ERROR("Unknown command %d", command); + break; } if (command == AT91C_EFC_FCMD_SPUI) { @@ -2571,18 +2570,18 @@ static void sam3_explain_ckgr_mor(struct sam3_chip *chip) chip->cfg.rc_freq = 0; if (rcen) { switch (v) { - case 0: - chip->cfg.rc_freq = 4 * 1000 * 1000; - break; - case 1: - chip->cfg.rc_freq = 8 * 1000 * 1000; - break; - case 2: - chip->cfg.rc_freq = 12 * 1000 * 1000; - break; - default: - chip->cfg.rc_freq = 0; - break; + case 0: + chip->cfg.rc_freq = 4 * 1000 * 1000; + break; + case 1: + chip->cfg.rc_freq = 8 * 1000 * 1000; + break; + case 2: + chip->cfg.rc_freq = 12 * 1000 * 1000; + break; + default: + chip->cfg.rc_freq = 0; + break; } } @@ -2683,30 +2682,30 @@ static void sam3_explain_mckr(struct sam3_chip *chip) css = sam3_reg_fieldname(chip, "CSS", chip->cfg.PMC_MCKR, 0, 2); switch (css & 3) { - case 0: - fin = chip->cfg.slow_freq; - cp = "slowclk"; - break; - case 1: - fin = chip->cfg.mainosc_freq; - cp = "mainosc"; - break; - case 2: - fin = chip->cfg.plla_freq; - cp = "plla"; - break; - case 3: - if (chip->cfg.CKGR_UCKR & (1 << 16)) { - fin = 480 * 1000 * 1000; - cp = "upll"; - } else { - fin = 0; - cp = "upll (*ERROR* UPLL is disabled)"; - } - break; - default: - assert(0); - break; + case 0: + fin = chip->cfg.slow_freq; + cp = "slowclk"; + break; + case 1: + fin = chip->cfg.mainosc_freq; + cp = "mainosc"; + break; + case 2: + fin = chip->cfg.plla_freq; + cp = "plla"; + break; + case 3: + if (chip->cfg.CKGR_UCKR & (1 << 16)) { + fin = 480 * 1000 * 1000; + cp = "upll"; + } else { + fin = 0; + cp = "upll (*ERROR* UPLL is disabled)"; + } + break; + default: + assert(0); + break; } LOG_USER("%s (%3.03f Mhz)", @@ -2714,41 +2713,41 @@ static void sam3_explain_mckr(struct sam3_chip *chip) _tomhz(fin)); pres = sam3_reg_fieldname(chip, "PRES", chip->cfg.PMC_MCKR, 4, 3); switch (pres & 0x07) { - case 0: - pdiv = 1; - cp = "selected clock"; - break; - case 1: - pdiv = 2; - cp = "clock/2"; - break; - case 2: - pdiv = 4; - cp = "clock/4"; - break; - case 3: - pdiv = 8; - cp = "clock/8"; - break; - case 4: - pdiv = 16; - cp = "clock/16"; - break; - case 5: - pdiv = 32; - cp = "clock/32"; - break; - case 6: - pdiv = 64; - cp = "clock/64"; - break; - case 7: - pdiv = 6; - cp = "clock/6"; - break; - default: - assert(0); - break; + case 0: + pdiv = 1; + cp = "selected clock"; + break; + case 1: + pdiv = 2; + cp = "clock/2"; + break; + case 2: + pdiv = 4; + cp = "clock/4"; + break; + case 3: + pdiv = 8; + cp = "clock/8"; + break; + case 4: + pdiv = 16; + cp = "clock/16"; + break; + case 5: + pdiv = 32; + cp = "clock/32"; + break; + case 6: + pdiv = 64; + cp = "clock/64"; + break; + case 7: + pdiv = 6; + cp = "clock/6"; + break; + default: + assert(0); + break; } LOG_USER("(%s)", cp); fin = fin / pdiv; @@ -3011,39 +3010,39 @@ FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command) } switch (bank->base) { - /* at91sam3s and at91sam3n series only has bank 0*/ - /* at91sam3u and at91sam3ax series has the same address for bank 0*/ - case FLASH_BANK_BASE_S: - case FLASH_BANK0_BASE_U: - bank->driver_priv = &chip->details.bank[0]; - bank->bank_number = 0; - chip->details.bank[0].chip = chip; - chip->details.bank[0].bank = bank; - break; + /* at91sam3s and at91sam3n series only has bank 0*/ + /* at91sam3u and at91sam3ax series has the same address for bank 0*/ + case FLASH_BANK_BASE_S: + case FLASH_BANK0_BASE_U: + bank->driver_priv = &chip->details.bank[0]; + bank->bank_number = 0; + chip->details.bank[0].chip = chip; + chip->details.bank[0].bank = bank; + break; - /* Bank 1 of at91sam3u or at91sam3ax series */ - case FLASH_BANK1_BASE_U: - case FLASH_BANK1_BASE_256K_AX: - case FLASH_BANK1_BASE_512K_AX: - bank->driver_priv = &chip->details.bank[1]; - bank->bank_number = 1; - chip->details.bank[1].chip = chip; - chip->details.bank[1].bank = bank; - break; + /* Bank 1 of at91sam3u or at91sam3ax series */ + case FLASH_BANK1_BASE_U: + case FLASH_BANK1_BASE_256K_AX: + case FLASH_BANK1_BASE_512K_AX: + bank->driver_priv = &chip->details.bank[1]; + bank->bank_number = 1; + chip->details.bank[1].chip = chip; + chip->details.bank[1].bank = bank; + break; - default: - LOG_ERROR("Address " TARGET_ADDR_FMT " invalid bank address (try 0x%08x or 0x%08x " - "[at91sam3u series] or 0x%08x [at91sam3s series] or " - "0x%08x [at91sam3n series] or 0x%08x or 0x%08x or 0x%08x[at91sam3ax series] )", - bank->base, - FLASH_BANK0_BASE_U, - FLASH_BANK1_BASE_U, - FLASH_BANK_BASE_S, - FLASH_BANK_BASE_N, - FLASH_BANK0_BASE_AX, - FLASH_BANK1_BASE_256K_AX, - FLASH_BANK1_BASE_512K_AX); - return ERROR_FAIL; + default: + LOG_ERROR("Address " TARGET_ADDR_FMT " invalid bank address (try 0x%08x or 0x%08x " + "[at91sam3u series] or 0x%08x [at91sam3s series] or " + "0x%08x [at91sam3n series] or 0x%08x or 0x%08x or 0x%08x[at91sam3ax series] )", + bank->base, + FLASH_BANK0_BASE_U, + FLASH_BANK1_BASE_U, + FLASH_BANK_BASE_S, + FLASH_BANK_BASE_N, + FLASH_BANK0_BASE_AX, + FLASH_BANK1_BASE_256K_AX, + FLASH_BANK1_BASE_512K_AX); + return ERROR_FAIL; } /* we initialize after probing. */ @@ -3574,22 +3573,22 @@ COMMAND_HANDLER(sam3_handle_gpnvm_command) } switch (CMD_ARGC) { - case 0: - goto showall; - case 1: + case 0: + goto showall; + case 1: + who = -1; + break; + case 2: + if ((strcmp(CMD_ARGV[0], "show") == 0) && (strcmp(CMD_ARGV[1], "all") == 0)) { who = -1; - break; - case 2: - if ((strcmp(CMD_ARGV[0], "show") == 0) && (strcmp(CMD_ARGV[1], "all") == 0)) { - who = -1; - } else { - uint32_t v32; - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32); - who = v32; - } - break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; + } else { + uint32_t v32; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32); + who = v32; + } + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } if (strcmp("show", CMD_ARGV[0]) == 0) { @@ -3641,26 +3640,26 @@ COMMAND_HANDLER(sam3_handle_slowclk_command) return ERROR_OK; switch (CMD_ARGC) { - case 0: - /* show */ - break; - case 1: - { - /* set */ - uint32_t v; - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v); - if (v > 200000) { - /* absurd slow clock of 200Khz? */ - command_print(CMD, "Absurd/illegal slow clock freq: %d\n", (int)(v)); - return ERROR_COMMAND_SYNTAX_ERROR; - } - chip->cfg.slow_freq = v; - break; - } - default: - /* error */ - command_print(CMD, "Too many parameters"); + case 0: + /* show */ + break; + case 1: + { + /* set */ + uint32_t v; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v); + if (v > 200000) { + /* absurd slow clock of 200Khz? */ + command_print(CMD, "Absurd/illegal slow clock freq: %d\n", (int)(v)); return ERROR_COMMAND_SYNTAX_ERROR; + } + chip->cfg.slow_freq = v; + break; + } + default: + /* error */ + command_print(CMD, "Too many parameters"); + return ERROR_COMMAND_SYNTAX_ERROR; } command_print(CMD, "Slowclk freq: %d.%03dkhz", (int)(chip->cfg.slow_freq / 1000), diff --git a/src/flash/nor/at91sam4.c b/src/flash/nor/at91sam4.c index 08f195577..dd3a1ca3f 100644 --- a/src/flash/nor/at91sam4.c +++ b/src/flash/nor/at91sam4.c @@ -1490,40 +1490,39 @@ do_retry: /* Check command & argument */ switch (command) { + case AT91C_EFC_FCMD_WP: + case AT91C_EFC_FCMD_WPL: + case AT91C_EFC_FCMD_EWP: + case AT91C_EFC_FCMD_EWPL: + /* case AT91C_EFC_FCMD_EPL: */ + case AT91C_EFC_FCMD_EPA: + case AT91C_EFC_FCMD_SLB: + case AT91C_EFC_FCMD_CLB: + n = (private->size_bytes / private->page_size); + if (argument >= n) + LOG_ERROR("*BUG*: Embedded flash has only %" PRIu32 " pages", n); + break; - case AT91C_EFC_FCMD_WP: - case AT91C_EFC_FCMD_WPL: - case AT91C_EFC_FCMD_EWP: - case AT91C_EFC_FCMD_EWPL: - /* case AT91C_EFC_FCMD_EPL: */ - case AT91C_EFC_FCMD_EPA: - case AT91C_EFC_FCMD_SLB: - case AT91C_EFC_FCMD_CLB: - n = (private->size_bytes / private->page_size); - if (argument >= n) - LOG_ERROR("*BUG*: Embedded flash has only %" PRIu32 " pages", n); - break; + case AT91C_EFC_FCMD_SFB: + case AT91C_EFC_FCMD_CFB: + if (argument >= private->chip->details.n_gpnvms) { + LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs", + private->chip->details.n_gpnvms); + } + break; - case AT91C_EFC_FCMD_SFB: - case AT91C_EFC_FCMD_CFB: - if (argument >= private->chip->details.n_gpnvms) { - LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs", - private->chip->details.n_gpnvms); - } - break; - - case AT91C_EFC_FCMD_GETD: - case AT91C_EFC_FCMD_EA: - case AT91C_EFC_FCMD_GLB: - case AT91C_EFC_FCMD_GFB: - case AT91C_EFC_FCMD_STUI: - case AT91C_EFC_FCMD_SPUI: - if (argument != 0) - LOG_ERROR("Argument is meaningless for cmd: %d", command); - break; - default: - LOG_ERROR("Unknown command %d", command); - break; + case AT91C_EFC_FCMD_GETD: + case AT91C_EFC_FCMD_EA: + case AT91C_EFC_FCMD_GLB: + case AT91C_EFC_FCMD_GFB: + case AT91C_EFC_FCMD_STUI: + case AT91C_EFC_FCMD_SPUI: + if (argument != 0) + LOG_ERROR("Argument is meaningless for cmd: %d", command); + break; + default: + LOG_ERROR("Unknown command %d", command); + break; } if (command == AT91C_EFC_FCMD_SPUI) { @@ -1678,21 +1677,21 @@ static int flashd_erase_pages(struct sam4_bank_private *private, LOG_DEBUG("Here"); uint8_t erase_pages; switch (num_pages) { - case 4: - erase_pages = 0x00; - break; - case 8: - erase_pages = 0x01; - break; - case 16: - erase_pages = 0x02; - break; - case 32: - erase_pages = 0x03; - break; - default: - erase_pages = 0x00; - break; + case 4: + erase_pages = 0x00; + break; + case 8: + erase_pages = 0x01; + break; + case 16: + erase_pages = 0x02; + break; + case 32: + erase_pages = 0x03; + break; + default: + erase_pages = 0x00; + break; } /* AT91C_EFC_FCMD_EPA @@ -2080,18 +2079,18 @@ static void sam4_explain_ckgr_mor(struct sam4_chip *chip) chip->cfg.rc_freq = 0; if (rcen) { switch (v) { - case 0: - chip->cfg.rc_freq = 4 * 1000 * 1000; - break; - case 1: - chip->cfg.rc_freq = 8 * 1000 * 1000; - break; - case 2: - chip->cfg.rc_freq = 12 * 1000 * 1000; - break; - default: - chip->cfg.rc_freq = 0; - break; + case 0: + chip->cfg.rc_freq = 4 * 1000 * 1000; + break; + case 1: + chip->cfg.rc_freq = 8 * 1000 * 1000; + break; + case 2: + chip->cfg.rc_freq = 12 * 1000 * 1000; + break; + default: + chip->cfg.rc_freq = 0; + break; } } @@ -2192,30 +2191,30 @@ static void sam4_explain_mckr(struct sam4_chip *chip) css = sam4_reg_fieldname(chip, "CSS", chip->cfg.PMC_MCKR, 0, 2); switch (css & 3) { - case 0: - fin = chip->cfg.slow_freq; - cp = "slowclk"; - break; - case 1: - fin = chip->cfg.mainosc_freq; - cp = "mainosc"; - break; - case 2: - fin = chip->cfg.plla_freq; - cp = "plla"; - break; - case 3: - if (chip->cfg.CKGR_UCKR & (1 << 16)) { - fin = 480 * 1000 * 1000; - cp = "upll"; - } else { - fin = 0; - cp = "upll (*ERROR* UPLL is disabled)"; - } - break; - default: - assert(0); - break; + case 0: + fin = chip->cfg.slow_freq; + cp = "slowclk"; + break; + case 1: + fin = chip->cfg.mainosc_freq; + cp = "mainosc"; + break; + case 2: + fin = chip->cfg.plla_freq; + cp = "plla"; + break; + case 3: + if (chip->cfg.CKGR_UCKR & (1 << 16)) { + fin = 480 * 1000 * 1000; + cp = "upll"; + } else { + fin = 0; + cp = "upll (*ERROR* UPLL is disabled)"; + } + break; + default: + assert(0); + break; } LOG_USER("%s (%3.03f Mhz)", @@ -2223,41 +2222,41 @@ static void sam4_explain_mckr(struct sam4_chip *chip) _tomhz(fin)); pres = sam4_reg_fieldname(chip, "PRES", chip->cfg.PMC_MCKR, 4, 3); switch (pres & 0x07) { - case 0: - pdiv = 1; - cp = "selected clock"; - break; - case 1: - pdiv = 2; - cp = "clock/2"; - break; - case 2: - pdiv = 4; - cp = "clock/4"; - break; - case 3: - pdiv = 8; - cp = "clock/8"; - break; - case 4: - pdiv = 16; - cp = "clock/16"; - break; - case 5: - pdiv = 32; - cp = "clock/32"; - break; - case 6: - pdiv = 64; - cp = "clock/64"; - break; - case 7: - pdiv = 6; - cp = "clock/6"; - break; - default: - assert(0); - break; + case 0: + pdiv = 1; + cp = "selected clock"; + break; + case 1: + pdiv = 2; + cp = "clock/2"; + break; + case 2: + pdiv = 4; + cp = "clock/4"; + break; + case 3: + pdiv = 8; + cp = "clock/8"; + break; + case 4: + pdiv = 16; + cp = "clock/16"; + break; + case 5: + pdiv = 32; + cp = "clock/32"; + break; + case 6: + pdiv = 64; + cp = "clock/64"; + break; + case 7: + pdiv = 6; + cp = "clock/6"; + break; + default: + assert(0); + break; } LOG_USER("(%s)", cp); fin = fin / pdiv; @@ -2504,32 +2503,32 @@ FLASH_BANK_COMMAND_HANDLER(sam4_flash_bank_command) } switch (bank->base) { - /* at91sam4s series only has bank 0*/ - /* at91sam4sd series has the same address for bank 0 (FLASH_BANK0_BASE_SD)*/ - case FLASH_BANK_BASE_S: - case FLASH_BANK_BASE_C: - bank->driver_priv = &chip->details.bank[0]; - bank->bank_number = 0; - chip->details.bank[0].chip = chip; - chip->details.bank[0].bank = bank; - break; + /* at91sam4s series only has bank 0*/ + /* at91sam4sd series has the same address for bank 0 (FLASH_BANK0_BASE_SD)*/ + case FLASH_BANK_BASE_S: + case FLASH_BANK_BASE_C: + bank->driver_priv = &chip->details.bank[0]; + bank->bank_number = 0; + chip->details.bank[0].chip = chip; + chip->details.bank[0].bank = bank; + break; - /* Bank 1 of at91sam4sd/at91sam4c32 series */ - case FLASH_BANK1_BASE_1024K_SD: - case FLASH_BANK1_BASE_2048K_SD: - case FLASH_BANK1_BASE_C32: - bank->driver_priv = &chip->details.bank[1]; - bank->bank_number = 1; - chip->details.bank[1].chip = chip; - chip->details.bank[1].bank = bank; - break; + /* Bank 1 of at91sam4sd/at91sam4c32 series */ + case FLASH_BANK1_BASE_1024K_SD: + case FLASH_BANK1_BASE_2048K_SD: + case FLASH_BANK1_BASE_C32: + bank->driver_priv = &chip->details.bank[1]; + bank->bank_number = 1; + chip->details.bank[1].chip = chip; + chip->details.bank[1].bank = bank; + break; - default: - LOG_ERROR("Address " TARGET_ADDR_FMT " invalid bank address (try 0x%08x" - "[at91sam4s series] )", - bank->base, - FLASH_BANK_BASE_S); - return ERROR_FAIL; + default: + LOG_ERROR("Address " TARGET_ADDR_FMT " invalid bank address (try 0x%08x" + "[at91sam4s series] )", + bank->base, + FLASH_BANK_BASE_S); + return ERROR_FAIL; } /* we initialize after probing. */ @@ -3122,22 +3121,22 @@ COMMAND_HANDLER(sam4_handle_gpnvm_command) } switch (CMD_ARGC) { - case 0: - goto showall; - case 1: + case 0: + goto showall; + case 1: + who = -1; + break; + case 2: + if ((strcmp(CMD_ARGV[0], "show") == 0) && (strcmp(CMD_ARGV[1], "all") == 0)) { who = -1; - break; - case 2: - if ((strcmp(CMD_ARGV[0], "show") == 0) && (strcmp(CMD_ARGV[1], "all") == 0)) { - who = -1; - } else { - uint32_t v32; - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32); - who = v32; - } - break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; + } else { + uint32_t v32; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32); + who = v32; + } + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } if (strcmp("show", CMD_ARGV[0]) == 0) { @@ -3189,26 +3188,26 @@ COMMAND_HANDLER(sam4_handle_slowclk_command) return ERROR_OK; switch (CMD_ARGC) { - case 0: - /* show */ - break; - case 1: - { - /* set */ - uint32_t v; - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v); - if (v > 200000) { - /* absurd slow clock of 200Khz? */ - command_print(CMD, "Absurd/illegal slow clock freq: %d\n", (int)(v)); - return ERROR_COMMAND_SYNTAX_ERROR; - } - chip->cfg.slow_freq = v; - break; - } - default: - /* error */ - command_print(CMD, "Too many parameters"); + case 0: + /* show */ + break; + case 1: + { + /* set */ + uint32_t v; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v); + if (v > 200000) { + /* absurd slow clock of 200Khz? */ + command_print(CMD, "Absurd/illegal slow clock freq: %d\n", (int)(v)); return ERROR_COMMAND_SYNTAX_ERROR; + } + chip->cfg.slow_freq = v; + break; + } + default: + /* error */ + command_print(CMD, "Too many parameters"); + return ERROR_COMMAND_SYNTAX_ERROR; } command_print(CMD, "Slowclk freq: %d.%03dkhz", (int)(chip->cfg.slow_freq / 1000), diff --git a/src/flash/nor/at91sam4l.c b/src/flash/nor/at91sam4l.c index ddf42a8c5..1db15377e 100644 --- a/src/flash/nor/at91sam4l.c +++ b/src/flash/nor/at91sam4l.c @@ -282,19 +282,19 @@ static int sam4l_probe(struct flash_bank *bank) chip->ram_kb = sam4l_ram_sizes[0xF & (id >> 16)]; switch (0xF & (id >> 8)) { - case 0x07: - chip->flash_kb = 128; - break; - case 0x09: - chip->flash_kb = 256; - break; - case 0x0A: - chip->flash_kb = 512; - break; - default: - LOG_ERROR("Unknown flash size (chip ID is %08" PRIx32 "), assuming 128K", id); - chip->flash_kb = 128; - break; + case 0x07: + chip->flash_kb = 128; + break; + case 0x09: + chip->flash_kb = 256; + break; + case 0x0A: + chip->flash_kb = 512; + break; + default: + LOG_ERROR("Unknown flash size (chip ID is %08" PRIx32 "), assuming 128K", id); + chip->flash_kb = 128; + break; } /* Retrieve the Flash parameters */ diff --git a/src/flash/nor/at91sam7.c b/src/flash/nor/at91sam7.c index b64864ad1..a4c92a93c 100644 --- a/src/flash/nor/at91sam7.c +++ b/src/flash/nor/at91sam7.c @@ -193,41 +193,41 @@ static void at91sam7_read_clock_info(struct flash_bank *bank) at91sam7_info->mck_valid = 0; at91sam7_info->mck_freq = 0; switch (mckr & PMC_MCKR_CSS) { - case 0: /* Slow Clock */ + case 0: /* Slow Clock */ + at91sam7_info->mck_valid = 1; + tmp = RC_FREQ; + break; + + case 1: /* Main Clock */ + if ((mcfr & CKGR_MCFR_MAINRDY) && at91sam7_info->ext_freq == 0) { at91sam7_info->mck_valid = 1; - tmp = RC_FREQ; - break; + tmp = RC_FREQ / 16ul * (mcfr & 0xffff); + } else if (at91sam7_info->ext_freq != 0) { + at91sam7_info->mck_valid = 1; + tmp = at91sam7_info->ext_freq; + } + break; - case 1: /* Main Clock */ - if ((mcfr & CKGR_MCFR_MAINRDY) && at91sam7_info->ext_freq == 0) { - at91sam7_info->mck_valid = 1; - tmp = RC_FREQ / 16ul * (mcfr & 0xffff); - } else if (at91sam7_info->ext_freq != 0) { - at91sam7_info->mck_valid = 1; - tmp = at91sam7_info->ext_freq; - } - break; + case 2: /* Reserved */ + break; - case 2: /* Reserved */ - break; - - case 3: /* PLL Clock */ - if ((mcfr & CKGR_MCFR_MAINRDY) && at91sam7_info->ext_freq == 0) { - target_read_u32(target, CKGR_PLLR, &pllr); - if (!(pllr & CKGR_PLLR_DIV)) - break; /* 0 Hz */ - at91sam7_info->mck_valid = 1; - mainfreq = RC_FREQ / 16ul * (mcfr & 0xffff); - /* Integer arithmetic should have sufficient precision - * as long as PLL is properly configured. */ - tmp = mainfreq / (pllr & CKGR_PLLR_DIV)* - (((pllr & CKGR_PLLR_MUL) >> 16) + 1); - } else if ((at91sam7_info->ext_freq != 0) && ((pllr & CKGR_PLLR_DIV) != 0)) { - at91sam7_info->mck_valid = 1; - tmp = at91sam7_info->ext_freq / (pllr&CKGR_PLLR_DIV)* - (((pllr & CKGR_PLLR_MUL) >> 16) + 1); - } - break; + case 3: /* PLL Clock */ + if ((mcfr & CKGR_MCFR_MAINRDY) && at91sam7_info->ext_freq == 0) { + target_read_u32(target, CKGR_PLLR, &pllr); + if (!(pllr & CKGR_PLLR_DIV)) + break; /* 0 Hz */ + at91sam7_info->mck_valid = 1; + mainfreq = RC_FREQ / 16ul * (mcfr & 0xffff); + /* Integer arithmetic should have sufficient precision + * as long as PLL is properly configured. */ + tmp = mainfreq / (pllr & CKGR_PLLR_DIV) * + (((pllr & CKGR_PLLR_MUL) >> 16) + 1); + } else if ((at91sam7_info->ext_freq != 0) && ((pllr & CKGR_PLLR_DIV) != 0)) { + at91sam7_info->mck_valid = 1; + tmp = at91sam7_info->ext_freq / (pllr & CKGR_PLLR_DIV) * + (((pllr & CKGR_PLLR_MUL) >> 16) + 1); + } + break; } /* Prescaler adjust */ @@ -415,130 +415,130 @@ static int at91sam7_read_part_info(struct flash_bank *bank) /* check flash size */ switch ((cidr >> 8)&0x000F) { - case FLASH_SIZE_8KB: - break; + case FLASH_SIZE_8KB: + break; - case FLASH_SIZE_16KB: - banks_num = 1; - sectors_num = 8; - pages_per_sector = 32; - page_size = 64; - base_address = 0x00100000; - if (arch == 0x70) { - num_nvmbits = 2; - target_name_t = "AT91SAM7S161/16"; - } - break; + case FLASH_SIZE_16KB: + banks_num = 1; + sectors_num = 8; + pages_per_sector = 32; + page_size = 64; + base_address = 0x00100000; + if (arch == 0x70) { + num_nvmbits = 2; + target_name_t = "AT91SAM7S161/16"; + } + break; - case FLASH_SIZE_32KB: - banks_num = 1; - sectors_num = 8; - pages_per_sector = 32; - page_size = 128; - base_address = 0x00100000; - if (arch == 0x70) { - num_nvmbits = 2; - target_name_t = "AT91SAM7S321/32"; - } - if (arch == 0x72) { - num_nvmbits = 3; - target_name_t = "AT91SAM7SE32"; - } - break; + case FLASH_SIZE_32KB: + banks_num = 1; + sectors_num = 8; + pages_per_sector = 32; + page_size = 128; + base_address = 0x00100000; + if (arch == 0x70) { + num_nvmbits = 2; + target_name_t = "AT91SAM7S321/32"; + } + if (arch == 0x72) { + num_nvmbits = 3; + target_name_t = "AT91SAM7SE32"; + } + break; - case FLASH_SIZE_64KB: - banks_num = 1; - sectors_num = 16; - pages_per_sector = 32; - page_size = 128; - base_address = 0x00100000; - if (arch == 0x70) { - num_nvmbits = 2; - target_name_t = "AT91SAM7S64"; - } - break; + case FLASH_SIZE_64KB: + banks_num = 1; + sectors_num = 16; + pages_per_sector = 32; + page_size = 128; + base_address = 0x00100000; + if (arch == 0x70) { + num_nvmbits = 2; + target_name_t = "AT91SAM7S64"; + } + break; - case FLASH_SIZE_128KB: - banks_num = 1; - sectors_num = 8; - pages_per_sector = 64; - page_size = 256; - base_address = 0x00100000; - if (arch == 0x70) { - num_nvmbits = 2; - target_name_t = "AT91SAM7S128"; - } - if (arch == 0x71) { - num_nvmbits = 3; - target_name_t = "AT91SAM7XC128"; - } - if (arch == 0x72) { - num_nvmbits = 3; - target_name_t = "AT91SAM7SE128"; - } - if (arch == 0x75) { - num_nvmbits = 3; - target_name_t = "AT91SAM7X128"; - } - break; + case FLASH_SIZE_128KB: + banks_num = 1; + sectors_num = 8; + pages_per_sector = 64; + page_size = 256; + base_address = 0x00100000; + if (arch == 0x70) { + num_nvmbits = 2; + target_name_t = "AT91SAM7S128"; + } + if (arch == 0x71) { + num_nvmbits = 3; + target_name_t = "AT91SAM7XC128"; + } + if (arch == 0x72) { + num_nvmbits = 3; + target_name_t = "AT91SAM7SE128"; + } + if (arch == 0x75) { + num_nvmbits = 3; + target_name_t = "AT91SAM7X128"; + } + break; - case FLASH_SIZE_256KB: - banks_num = 1; - sectors_num = 16; - pages_per_sector = 64; - page_size = 256; - base_address = 0x00100000; - if (arch == 0x60) { - num_nvmbits = 3; - target_name_t = "AT91SAM7A3"; - } - if (arch == 0x70) { - num_nvmbits = 2; - target_name_t = "AT91SAM7S256"; - } - if (arch == 0x71) { - num_nvmbits = 3; - target_name_t = "AT91SAM7XC256"; - } - if (arch == 0x72) { - num_nvmbits = 3; - target_name_t = "AT91SAM7SE256"; - } - if (arch == 0x75) { - num_nvmbits = 3; - target_name_t = "AT91SAM7X256"; - } - break; + case FLASH_SIZE_256KB: + banks_num = 1; + sectors_num = 16; + pages_per_sector = 64; + page_size = 256; + base_address = 0x00100000; + if (arch == 0x60) { + num_nvmbits = 3; + target_name_t = "AT91SAM7A3"; + } + if (arch == 0x70) { + num_nvmbits = 2; + target_name_t = "AT91SAM7S256"; + } + if (arch == 0x71) { + num_nvmbits = 3; + target_name_t = "AT91SAM7XC256"; + } + if (arch == 0x72) { + num_nvmbits = 3; + target_name_t = "AT91SAM7SE256"; + } + if (arch == 0x75) { + num_nvmbits = 3; + target_name_t = "AT91SAM7X256"; + } + break; - case FLASH_SIZE_512KB: - banks_num = 2; - sectors_num = 16; - pages_per_sector = 64; - page_size = 256; - base_address = 0x00100000; - if (arch == 0x70) { - num_nvmbits = 2; - target_name_t = "AT91SAM7S512"; - } - if (arch == 0x71) { - num_nvmbits = 3; - target_name_t = "AT91SAM7XC512"; - } - if (arch == 0x72) { - num_nvmbits = 3; - target_name_t = "AT91SAM7SE512"; - } - if (arch == 0x75) { - num_nvmbits = 3; - target_name_t = "AT91SAM7X512"; - } - break; + case FLASH_SIZE_512KB: + banks_num = 2; + sectors_num = 16; + pages_per_sector = 64; + page_size = 256; + base_address = 0x00100000; + if (arch == 0x70) { + num_nvmbits = 2; + target_name_t = "AT91SAM7S512"; + } + if (arch == 0x71) { + num_nvmbits = 3; + target_name_t = "AT91SAM7XC512"; + } + if (arch == 0x72) { + num_nvmbits = 3; + target_name_t = "AT91SAM7SE512"; + } + if (arch == 0x75) { + num_nvmbits = 3; + target_name_t = "AT91SAM7X512"; + } + break; - case FLASH_SIZE_1024KB: - break; + case FLASH_SIZE_1024KB: + break; - case FLASH_SIZE_2048KB: - break; + case FLASH_SIZE_2048KB: + break; } if (strcmp(target_name_t, "Unknown") == 0) { diff --git a/src/flash/nor/atsamv.c b/src/flash/nor/atsamv.c index c3b9a5dbd..de0b7dd1d 100644 --- a/src/flash/nor/atsamv.c +++ b/src/flash/nor/atsamv.c @@ -245,21 +245,21 @@ static int samv_erase_pages(struct target *target, { uint8_t erase_pages; switch (num_pages) { - case 4: - erase_pages = 0x00; - break; - case 8: - erase_pages = 0x01; - break; - case 16: - erase_pages = 0x02; - break; - case 32: - erase_pages = 0x03; - break; - default: - erase_pages = 0x00; - break; + case 4: + erase_pages = 0x00; + break; + case 8: + erase_pages = 0x01; + break; + case 16: + erase_pages = 0x02; + break; + case 32: + erase_pages = 0x03; + break; + default: + erase_pages = 0x00; + break; } /* SAMV_EFC_FCMD_EPA @@ -445,18 +445,18 @@ static int samv_probe(struct flash_bank *bank) uint8_t nvm_size_code = (device_id >> 8) & 0xf; switch (nvm_size_code) { - case 10: - bank->size = 512 * 1024; - break; - case 12: - bank->size = 1024 * 1024; - break; - case 14: - bank->size = 2048 * 1024; - break; - default: - LOG_ERROR("unrecognized flash size code: %d", nvm_size_code); - return ERROR_FAIL; + case 10: + bank->size = 512 * 1024; + break; + case 12: + bank->size = 1024 * 1024; + break; + case 14: + bank->size = 2048 * 1024; + break; + default: + LOG_ERROR("unrecognized flash size code: %d", nvm_size_code); + return ERROR_FAIL; } struct samv_flash_bank *samv_info = bank->driver_priv; @@ -816,22 +816,22 @@ COMMAND_HANDLER(samv_handle_gpnvm_command) int who = 0; switch (CMD_ARGC) { - case 0: - goto showall; - case 1: + case 0: + goto showall; + case 1: + who = -1; + break; + case 2: + if (!strcmp(CMD_ARGV[0], "show") && !strcmp(CMD_ARGV[1], "all")) { who = -1; - break; - case 2: - if (!strcmp(CMD_ARGV[0], "show") && !strcmp(CMD_ARGV[1], "all")) { - who = -1; - } else { - uint32_t v32; - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32); - who = v32; - } - break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; + } else { + uint32_t v32; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32); + who = v32; + } + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } unsigned int v = 0; diff --git a/src/flash/nor/cc26xx.c b/src/flash/nor/cc26xx.c index 765a32718..f7c2011be 100644 --- a/src/flash/nor/cc26xx.c +++ b/src/flash/nor/cc26xx.c @@ -51,22 +51,22 @@ static uint32_t cc26xx_device_type(uint32_t icepick_id, uint32_t user_id) uint32_t device_type = 0; switch (icepick_id & ICEPICK_ID_MASK) { - case CC26X0_ICEPICK_ID: - device_type = CC26X0_TYPE; - break; - case CC26X1_ICEPICK_ID: - device_type = CC26X1_TYPE; - break; - case CC13X0_ICEPICK_ID: - device_type = CC13X0_TYPE; - break; - case CC13X2_CC26X2_ICEPICK_ID: - default: - if ((user_id & USER_ID_CC13_MASK) != 0) - device_type = CC13X2_TYPE; - else - device_type = CC26X2_TYPE; - break; + case CC26X0_ICEPICK_ID: + device_type = CC26X0_TYPE; + break; + case CC26X1_ICEPICK_ID: + device_type = CC26X1_TYPE; + break; + case CC13X0_ICEPICK_ID: + device_type = CC13X0_TYPE; + break; + case CC13X2_CC26X2_ICEPICK_ID: + default: + if ((user_id & USER_ID_CC13_MASK) != 0) + device_type = CC13X2_TYPE; + else + device_type = CC26X2_TYPE; + break; } return device_type; @@ -77,17 +77,17 @@ static uint32_t cc26xx_sector_length(uint32_t icepick_id) uint32_t sector_length; switch (icepick_id & ICEPICK_ID_MASK) { - case CC26X0_ICEPICK_ID: - case CC26X1_ICEPICK_ID: - case CC13X0_ICEPICK_ID: - /* Chameleon family device */ - sector_length = CC26X0_SECTOR_LENGTH; - break; - case CC13X2_CC26X2_ICEPICK_ID: - default: - /* Agama family device */ - sector_length = CC26X2_SECTOR_LENGTH; - break; + case CC26X0_ICEPICK_ID: + case CC26X1_ICEPICK_ID: + case CC13X0_ICEPICK_ID: + /* Chameleon family device */ + sector_length = CC26X0_SECTOR_LENGTH; + break; + case CC13X2_CC26X2_ICEPICK_ID: + default: + /* Agama family device */ + sector_length = CC26X2_SECTOR_LENGTH; + break; } return sector_length; @@ -422,31 +422,31 @@ static int cc26xx_probe(struct flash_bank *bank) /* Set up appropriate flash helper algorithm */ switch (cc26xx_bank->icepick_id & ICEPICK_ID_MASK) { - case CC26X0_ICEPICK_ID: - case CC26X1_ICEPICK_ID: - case CC13X0_ICEPICK_ID: - /* Chameleon family device */ - cc26xx_bank->algo_code = cc26x0_algo; - cc26xx_bank->algo_size = sizeof(cc26x0_algo); - cc26xx_bank->algo_working_size = CC26X0_WORKING_SIZE; - cc26xx_bank->buffer_addr[0] = CC26X0_ALGO_BUFFER_0; - cc26xx_bank->buffer_addr[1] = CC26X0_ALGO_BUFFER_1; - cc26xx_bank->params_addr[0] = CC26X0_ALGO_PARAMS_0; - cc26xx_bank->params_addr[1] = CC26X0_ALGO_PARAMS_1; - max_sectors = CC26X0_MAX_SECTORS; - break; - case CC13X2_CC26X2_ICEPICK_ID: - default: - /* Agama family device */ - cc26xx_bank->algo_code = cc26x2_algo; - cc26xx_bank->algo_size = sizeof(cc26x2_algo); - cc26xx_bank->algo_working_size = CC26X2_WORKING_SIZE; - cc26xx_bank->buffer_addr[0] = CC26X2_ALGO_BUFFER_0; - cc26xx_bank->buffer_addr[1] = CC26X2_ALGO_BUFFER_1; - cc26xx_bank->params_addr[0] = CC26X2_ALGO_PARAMS_0; - cc26xx_bank->params_addr[1] = CC26X2_ALGO_PARAMS_1; - max_sectors = CC26X2_MAX_SECTORS; - break; + case CC26X0_ICEPICK_ID: + case CC26X1_ICEPICK_ID: + case CC13X0_ICEPICK_ID: + /* Chameleon family device */ + cc26xx_bank->algo_code = cc26x0_algo; + cc26xx_bank->algo_size = sizeof(cc26x0_algo); + cc26xx_bank->algo_working_size = CC26X0_WORKING_SIZE; + cc26xx_bank->buffer_addr[0] = CC26X0_ALGO_BUFFER_0; + cc26xx_bank->buffer_addr[1] = CC26X0_ALGO_BUFFER_1; + cc26xx_bank->params_addr[0] = CC26X0_ALGO_PARAMS_0; + cc26xx_bank->params_addr[1] = CC26X0_ALGO_PARAMS_1; + max_sectors = CC26X0_MAX_SECTORS; + break; + case CC13X2_CC26X2_ICEPICK_ID: + default: + /* Agama family device */ + cc26xx_bank->algo_code = cc26x2_algo; + cc26xx_bank->algo_size = sizeof(cc26x2_algo); + cc26xx_bank->algo_working_size = CC26X2_WORKING_SIZE; + cc26xx_bank->buffer_addr[0] = CC26X2_ALGO_BUFFER_0; + cc26xx_bank->buffer_addr[1] = CC26X2_ALGO_BUFFER_1; + cc26xx_bank->params_addr[0] = CC26X2_ALGO_PARAMS_0; + cc26xx_bank->params_addr[1] = CC26X2_ALGO_PARAMS_1; + max_sectors = CC26X2_MAX_SECTORS; + break; } retval = target_read_u32(target, CC26XX_FLASH_SIZE_INFO, &value); @@ -500,25 +500,25 @@ static int cc26xx_info(struct flash_bank *bank, struct command_invocation *cmd) const char *device; switch (cc26xx_bank->device_type) { - case CC26X0_TYPE: - device = "CC26x0"; - break; - case CC26X1_TYPE: - device = "CC26x1"; - break; - case CC13X0_TYPE: - device = "CC13x0"; - break; - case CC13X2_TYPE: - device = "CC13x2"; - break; - case CC26X2_TYPE: - device = "CC26x2"; - break; - case CC26XX_NO_TYPE: - default: - device = "Unrecognized"; - break; + case CC26X0_TYPE: + device = "CC26x0"; + break; + case CC26X1_TYPE: + device = "CC26x1"; + break; + case CC13X0_TYPE: + device = "CC13x0"; + break; + case CC13X2_TYPE: + device = "CC13x2"; + break; + case CC26X2_TYPE: + device = "CC26x2"; + break; + case CC26XX_NO_TYPE: + default: + device = "Unrecognized"; + break; } command_print_sameline(cmd, diff --git a/src/flash/nor/cfi.c b/src/flash/nor/cfi.c index fdc1682c3..108b66750 100644 --- a/src/flash/nor/cfi.c +++ b/src/flash/nor/cfi.c @@ -945,14 +945,14 @@ int cfi_erase(struct flash_bank *bank, unsigned int first, return ERROR_FLASH_BANK_NOT_PROBED; switch (cfi_info->pri_id) { - case 1: - case 3: - return cfi_intel_erase(bank, first, last); - case 2: - return cfi_spansion_erase(bank, first, last); - default: - LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); - break; + case 1: + case 3: + return cfi_intel_erase(bank, first, last); + case 2: + return cfi_spansion_erase(bank, first, last); + default: + LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); + break; } return ERROR_OK; @@ -1084,12 +1084,12 @@ int cfi_protect(struct flash_bank *bank, int set, unsigned int first, return ERROR_FLASH_BANK_NOT_PROBED; switch (cfi_info->pri_id) { - case 1: - case 3: - return cfi_intel_protect(bank, set, first, last); - default: - LOG_WARNING("protect: cfi primary command set %i unsupported", cfi_info->pri_id); - return ERROR_OK; + case 1: + case 3: + return cfi_intel_protect(bank, set, first, last); + default: + LOG_WARNING("protect: cfi primary command set %i unsupported", cfi_info->pri_id); + return ERROR_OK; } } @@ -1100,16 +1100,16 @@ static uint32_t cfi_command_val(struct flash_bank *bank, uint8_t cmd) uint8_t buf[CFI_MAX_BUS_WIDTH]; cfi_command(bank, cmd, buf); switch (bank->bus_width) { - case 1: - return buf[0]; - case 2: - return target_buffer_get_u16(target, buf); - case 4: - return target_buffer_get_u32(target, buf); - default: - LOG_ERROR("Unsupported bank buswidth %u, can't do block memory writes", - bank->bus_width); - return 0; + case 1: + return buf[0]; + case 2: + return target_buffer_get_u16(target, buf); + case 4: + return target_buffer_get_u32(target, buf); + default: + LOG_ERROR("Unsupported bank buswidth %u, can't do block memory writes", + bank->bus_width); + return 0; } } @@ -1214,22 +1214,22 @@ static int cfi_intel_write_block(struct flash_bank *bank, const uint8_t *buffer, /* prepare algorithm code for target endian */ switch (bank->bus_width) { - case 1: - target_code_src = word_8_code; - target_code_size = sizeof(word_8_code); - break; - case 2: - target_code_src = word_16_code; - target_code_size = sizeof(word_16_code); - break; - case 4: - target_code_src = word_32_code; - target_code_size = sizeof(word_32_code); - break; - default: - LOG_ERROR("Unsupported bank buswidth %u, can't do block memory writes", - bank->bus_width); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + case 1: + target_code_src = word_8_code; + target_code_size = sizeof(word_8_code); + break; + case 2: + target_code_src = word_16_code; + target_code_size = sizeof(word_16_code); + break; + case 4: + target_code_src = word_32_code; + target_code_size = sizeof(word_32_code); + break; + default: + LOG_ERROR("Unsupported bank buswidth %u, can't do block memory writes", + bank->bus_width); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } /* flash write code */ @@ -1448,22 +1448,22 @@ static int cfi_spansion_write_block_mips(struct flash_bank *bank, const uint8_t const uint32_t *target_code_src = NULL; switch (bank->bus_width) { - case 2: - /* Check for DQ5 support */ - if (cfi_info->status_poll_mask & (1 << 5)) { - target_code_src = mips_word_16_code; - target_code_size = sizeof(mips_word_16_code); - } else { - LOG_ERROR("Need DQ5 support"); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - /* target_code_src = mips_word_16_code_dq7only; */ - /* target_code_size = sizeof(mips_word_16_code_dq7only); */ - } - break; - default: - LOG_ERROR("Unsupported bank buswidth %u, can't do block memory writes", - bank->bus_width); + case 2: + /* Check for DQ5 support */ + if (cfi_info->status_poll_mask & (1 << 5)) { + target_code_src = mips_word_16_code; + target_code_size = sizeof(mips_word_16_code); + } else { + LOG_ERROR("Need DQ5 support"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + /* target_code_src = mips_word_16_code_dq7only; */ + /* target_code_size = sizeof(mips_word_16_code_dq7only); */ + } + break; + default: + LOG_ERROR("Unsupported bank buswidth %u, can't do block memory writes", + bank->bus_width); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } /* flash write code */ @@ -1800,49 +1800,49 @@ static int cfi_spansion_write_block(struct flash_bank *bank, const uint8_t *buff const uint32_t *target_code_src = NULL; switch (bank->bus_width) { - case 1: + case 1: + if (is_armv7m(target_to_armv7m(target))) { + LOG_ERROR("Unknown ARM architecture"); + return ERROR_FAIL; + } + target_code_src = armv4_5_word_8_code; + target_code_size = sizeof(armv4_5_word_8_code); + break; + case 2: + /* Check for DQ5 support */ + if (cfi_info->status_poll_mask & (1 << 5)) { if (is_armv7m(target_to_armv7m(target))) { - LOG_ERROR("Unknown ARM architecture"); - return ERROR_FAIL; + /* armv7m target */ + target_code_src = armv7m_word_16_code; + target_code_size = sizeof(armv7m_word_16_code); + } else { /* armv4_5 target */ + target_code_src = armv4_5_word_16_code; + target_code_size = sizeof(armv4_5_word_16_code); } - target_code_src = armv4_5_word_8_code; - target_code_size = sizeof(armv4_5_word_8_code); - break; - case 2: - /* Check for DQ5 support */ - if (cfi_info->status_poll_mask & (1 << 5)) { - if (is_armv7m(target_to_armv7m(target))) { - /* armv7m target */ - target_code_src = armv7m_word_16_code; - target_code_size = sizeof(armv7m_word_16_code); - } else { /* armv4_5 target */ - target_code_src = armv4_5_word_16_code; - target_code_size = sizeof(armv4_5_word_16_code); - } - } else { - /* No DQ5 support. Use DQ7 DATA# polling only. */ - if (is_armv7m(target_to_armv7m(target))) { - /* armv7m target */ - target_code_src = armv7m_word_16_code_dq7only; - target_code_size = sizeof(armv7m_word_16_code_dq7only); - } else { /* armv4_5 target */ - target_code_src = armv4_5_word_16_code_dq7only; - target_code_size = sizeof(armv4_5_word_16_code_dq7only); - } - } - break; - case 4: + } else { + /* No DQ5 support. Use DQ7 DATA# polling only. */ if (is_armv7m(target_to_armv7m(target))) { - LOG_ERROR("Unknown ARM architecture"); - return ERROR_FAIL; + /* armv7m target */ + target_code_src = armv7m_word_16_code_dq7only; + target_code_size = sizeof(armv7m_word_16_code_dq7only); + } else { /* armv4_5 target */ + target_code_src = armv4_5_word_16_code_dq7only; + target_code_size = sizeof(armv4_5_word_16_code_dq7only); } - target_code_src = armv4_5_word_32_code; - target_code_size = sizeof(armv4_5_word_32_code); - break; - default: - LOG_ERROR("Unsupported bank buswidth %u, can't do block memory writes", - bank->bus_width); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + break; + case 4: + if (is_armv7m(target_to_armv7m(target))) { + LOG_ERROR("Unknown ARM architecture"); + return ERROR_FAIL; + } + target_code_src = armv4_5_word_32_code; + target_code_size = sizeof(armv4_5_word_32_code); + break; + default: + LOG_ERROR("Unsupported bank buswidth %u, can't do block memory writes", + bank->bus_width); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } /* flash write code */ @@ -2172,14 +2172,14 @@ int cfi_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address) struct cfi_flash_bank *cfi_info = bank->driver_priv; switch (cfi_info->pri_id) { - case 1: - case 3: - return cfi_intel_write_word(bank, word, address); - case 2: - return cfi_spansion_write_word(bank, word, address); - default: - LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); - break; + case 1: + case 3: + return cfi_intel_write_word(bank, word, address); + case 2: + return cfi_spansion_write_word(bank, word, address); + default: + LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); + break; } return ERROR_FLASH_OPERATION_FAILED; @@ -2197,14 +2197,14 @@ static int cfi_write_words(struct flash_bank *bank, const uint8_t *word, } switch (cfi_info->pri_id) { - case 1: - case 3: - return cfi_intel_write_words(bank, word, wordcount, address); - case 2: - return cfi_spansion_write_words(bank, word, wordcount, address); - default: - LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); - break; + case 1: + case 3: + return cfi_intel_write_words(bank, word, wordcount, address); + case 2: + return cfi_spansion_write_words(bank, word, wordcount, address); + default: + LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); + break; } return ERROR_FLASH_OPERATION_FAILED; @@ -2345,18 +2345,18 @@ static int cfi_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t of /* handle blocks of bus_size aligned bytes */ blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */ switch (cfi_info->pri_id) { - /* try block writes (fails without working area) */ - case 1: - case 3: - retval = cfi_intel_write_block(bank, buffer, write_p, blk_count); - break; - case 2: - retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count); - break; - default: - LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); - retval = ERROR_FLASH_OPERATION_FAILED; - break; + /* try block writes (fails without working area) */ + case 1: + case 3: + retval = cfi_intel_write_block(bank, buffer, write_p, blk_count); + break; + case 2: + retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count); + break; + default: + LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); + retval = ERROR_FLASH_OPERATION_FAILED; + break; } if (retval == ERROR_OK) { /* Increment pointers and decrease count on successful block write */ @@ -2581,22 +2581,22 @@ int cfi_probe(struct flash_bank *bank) if (retval != ERROR_OK) return retval; switch (bank->chip_width) { - case 1: - cfi_info->manufacturer = *value_buf0; - cfi_info->device_id = *value_buf1; - break; - case 2: - cfi_info->manufacturer = target_buffer_get_u16(target, value_buf0); - cfi_info->device_id = target_buffer_get_u16(target, value_buf1); - break; - case 4: - cfi_info->manufacturer = target_buffer_get_u32(target, value_buf0); - cfi_info->device_id = target_buffer_get_u32(target, value_buf1); - break; - default: - LOG_ERROR("Unsupported bank chipwidth %u, can't probe memory", - bank->chip_width); - return ERROR_FLASH_OPERATION_FAILED; + case 1: + cfi_info->manufacturer = *value_buf0; + cfi_info->device_id = *value_buf1; + break; + case 2: + cfi_info->manufacturer = target_buffer_get_u16(target, value_buf0); + cfi_info->device_id = target_buffer_get_u16(target, value_buf1); + break; + case 4: + cfi_info->manufacturer = target_buffer_get_u32(target, value_buf0); + cfi_info->device_id = target_buffer_get_u32(target, value_buf1); + break; + default: + LOG_ERROR("Unsupported bank chipwidth %u, can't probe memory", + bank->chip_width); + return ERROR_FLASH_OPERATION_FAILED; } LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x", @@ -2734,25 +2734,25 @@ int cfi_probe(struct flash_bank *bank) * the sector layout to be able to apply fixups */ switch (cfi_info->pri_id) { - /* Intel command set (standard and extended) */ - case 0x0001: - case 0x0003: - cfi_read_intel_pri_ext(bank); - break; - /* AMD/Spansion, Atmel, ... command set */ - case 0x0002: - cfi_info->status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7; /* - *default - *for - *all - *CFI - *flashes - **/ - cfi_read_0002_pri_ext(bank); - break; - default: - LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); - break; + /* Intel command set (standard and extended) */ + case 0x0001: + case 0x0003: + cfi_read_intel_pri_ext(bank); + break; + /* AMD/Spansion, Atmel, ... command set */ + case 0x0002: + cfi_info->status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7; /* + *default + *for + *all + *CFI + *flashes + **/ + cfi_read_0002_pri_ext(bank); + break; + default: + LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); + break; } /* return to read array mode @@ -2798,18 +2798,18 @@ int cfi_probe(struct flash_bank *bank) /* apply fixups depending on the primary command set */ switch (cfi_info->pri_id) { - /* Intel command set (standard and extended) */ - case 0x0001: - case 0x0003: - cfi_fixup(bank, cfi_0001_fixups); - break; - /* AMD/Spansion, Atmel, ... command set */ - case 0x0002: - cfi_fixup(bank, cfi_0002_fixups); - break; - default: - LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); - break; + /* Intel command set (standard and extended) */ + case 0x0001: + case 0x0003: + cfi_fixup(bank, cfi_0001_fixups); + break; + /* AMD/Spansion, Atmel, ... command set */ + case 0x0002: + cfi_fixup(bank, cfi_0002_fixups); + break; + default: + LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); + break; } if ((cfi_info->dev_size * bank->bus_width / bank->chip_width) != bank->size) { @@ -2939,14 +2939,14 @@ int cfi_protect_check(struct flash_bank *bank) return ERROR_FLASH_BANK_NOT_PROBED; switch (cfi_info->pri_id) { - case 1: - case 3: - return cfi_intel_protect_check(bank); - case 2: - return cfi_spansion_protect_check(bank); - default: - LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); - break; + case 1: + case 3: + return cfi_intel_protect_check(bank); + case 2: + return cfi_spansion_protect_check(bank); + default: + LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); + break; } return ERROR_OK; @@ -3011,16 +3011,16 @@ int cfi_get_info(struct flash_bank *bank, struct command_invocation *cmd) 1 << cfi_info->max_buf_write_size); switch (cfi_info->pri_id) { - case 1: - case 3: - cfi_intel_info(bank, cmd); - break; - case 2: - cfi_spansion_info(bank, cmd); - break; - default: - LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); - break; + case 1: + case 3: + cfi_intel_info(bank, cmd); + break; + case 2: + cfi_spansion_info(bank, cmd); + break; + default: + LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); + break; } return ERROR_OK; diff --git a/src/flash/nor/efm32.c b/src/flash/nor/efm32.c index b011a69c7..e40286791 100644 --- a/src/flash/nor/efm32.c +++ b/src/flash/nor/efm32.c @@ -88,14 +88,14 @@ enum efm32_bank_index { static int efm32x_get_bank_index(target_addr_t base) { switch (base) { - case EFM32_FLASH_BASE: - return EFM32_BANK_INDEX_MAIN; - case EFM32_MSC_USER_DATA: - return EFM32_BANK_INDEX_USER_DATA; - case EFM32_MSC_LOCK_BITS: - return EFM32_BANK_INDEX_LOCK_BITS; - default: - return ERROR_FAIL; + case EFM32_FLASH_BASE: + return EFM32_BANK_INDEX_MAIN; + case EFM32_MSC_USER_DATA: + return EFM32_BANK_INDEX_USER_DATA; + case EFM32_MSC_LOCK_BITS: + return EFM32_BANK_INDEX_LOCK_BITS; + default: + return ERROR_FAIL; } } @@ -282,14 +282,14 @@ static int efm32x_read_info(struct flash_bank *bank) } switch (efm32_info->family_data->series) { - case 0: - efm32x_info->reg_base = EFM32_MSC_REGBASE; - efm32x_info->reg_lock = EFM32_MSC_REG_LOCK; - break; - case 1: - efm32x_info->reg_base = EFM32_MSC_REGBASE_SERIES1; - efm32x_info->reg_lock = EFM32_MSC_REG_LOCK_SERIES1; - break; + case 0: + efm32x_info->reg_base = EFM32_MSC_REGBASE; + efm32x_info->reg_lock = EFM32_MSC_REG_LOCK; + break; + case 1: + efm32x_info->reg_base = EFM32_MSC_REGBASE_SERIES1; + efm32x_info->reg_lock = EFM32_MSC_REG_LOCK_SERIES1; + break; } if (efm32_info->family_data->msc_regbase != 0) @@ -662,18 +662,18 @@ static int efm32x_get_page_lock(struct flash_bank *bank, size_t page) uint32_t mask = 0; switch (bank->base) { - case EFM32_FLASH_BASE: - dw = efm32x_info->lb_page[page >> 5]; - mask = 1 << (page & 0x1f); - break; - case EFM32_MSC_USER_DATA: - dw = efm32x_info->lb_page[126]; - mask = 0x1; - break; - case EFM32_MSC_LOCK_BITS: - dw = efm32x_info->lb_page[126]; - mask = 0x2; - break; + case EFM32_FLASH_BASE: + dw = efm32x_info->lb_page[page >> 5]; + mask = 1 << (page & 0x1f); + break; + case EFM32_MSC_USER_DATA: + dw = efm32x_info->lb_page[126]; + mask = 0x1; + break; + case EFM32_MSC_LOCK_BITS: + dw = efm32x_info->lb_page[126]; + mask = 0x2; + break; } return (dw & mask) ? 0 : 1; diff --git a/src/flash/nor/em357.c b/src/flash/nor/em357.c index a41b5f8b7..cf005ca22 100644 --- a/src/flash/nor/em357.c +++ b/src/flash/nor/em357.c @@ -670,36 +670,36 @@ static int em357_probe(struct flash_bank *bank) em357_info->probed = false; switch (bank->size) { - case 0x10000: - /* 64k -- 64 1k pages */ - num_pages = 64; - page_size = 1024; - break; - case 0x20000: - /* 128k -- 128 1k pages */ - num_pages = 128; - page_size = 1024; - break; - case 0x30000: - /* 192k -- 96 2k pages */ - num_pages = 96; - page_size = 2048; - break; - case 0x40000: - /* 256k -- 128 2k pages */ - num_pages = 128; - page_size = 2048; - break; - case 0x80000: - /* 512k -- 256 2k pages */ - num_pages = 256; - page_size = 2048; - break; - default: - LOG_WARNING("No size specified for em357 flash driver, assuming 192k!"); - num_pages = 96; - page_size = 2048; - break; + case 0x10000: + /* 64k -- 64 1k pages */ + num_pages = 64; + page_size = 1024; + break; + case 0x20000: + /* 128k -- 128 1k pages */ + num_pages = 128; + page_size = 1024; + break; + case 0x30000: + /* 192k -- 96 2k pages */ + num_pages = 96; + page_size = 2048; + break; + case 0x40000: + /* 256k -- 128 2k pages */ + num_pages = 128; + page_size = 2048; + break; + case 0x80000: + /* 512k -- 256 2k pages */ + num_pages = 256; + page_size = 2048; + break; + default: + LOG_WARNING("No size specified for em357 flash driver, assuming 192k!"); + num_pages = 96; + page_size = 2048; + break; } /* Enable FPEC CLK */ diff --git a/src/flash/nor/kinetis.c b/src/flash/nor/kinetis.c index 85c306bd4..82e68de3f 100644 --- a/src/flash/nor/kinetis.c +++ b/src/flash/nor/kinetis.c @@ -2145,24 +2145,24 @@ static int kinetis_probe_chip_s32k(struct kinetis_chip *k_chip) k_chip->max_flash_prog_size = 512; switch (k_chip->sim_sdid & KINETIS_SDID_S32K_DERIVATE_MASK) { - case KINETIS_SDID_S32K_DERIVATE_KXX6: - /* S32K116 CPU 48Mhz Flash 128KB RAM 17KB+2KB */ - /* Non-Interleaved */ - k_chip->pflash_size = 128 << 10; - k_chip->pflash_sector_size = 2 << 10; - /* Non-Interleaved */ - k_chip->nvm_size = 32 << 10; - k_chip->nvm_sector_size = 2 << 10; - break; - case KINETIS_SDID_S32K_DERIVATE_KXX8: - /* S32K118 CPU 80Mhz Flash 256KB+32KB RAM 32KB+4KB */ - /* Non-Interleaved */ - k_chip->pflash_size = 256 << 10; - k_chip->pflash_sector_size = 2 << 10; - /* Non-Interleaved */ - k_chip->nvm_size = 32 << 10; - k_chip->nvm_sector_size = 2 << 10; - break; + case KINETIS_SDID_S32K_DERIVATE_KXX6: + /* S32K116 CPU 48Mhz Flash 128KB RAM 17KB+2KB */ + /* Non-Interleaved */ + k_chip->pflash_size = 128 << 10; + k_chip->pflash_sector_size = 2 << 10; + /* Non-Interleaved */ + k_chip->nvm_size = 32 << 10; + k_chip->nvm_sector_size = 2 << 10; + break; + case KINETIS_SDID_S32K_DERIVATE_KXX8: + /* S32K118 CPU 80Mhz Flash 256KB+32KB RAM 32KB+4KB */ + /* Non-Interleaved */ + k_chip->pflash_size = 256 << 10; + k_chip->pflash_sector_size = 2 << 10; + /* Non-Interleaved */ + k_chip->nvm_size = 32 << 10; + k_chip->nvm_sector_size = 2 << 10; + break; } break; diff --git a/src/flash/nor/kinetis_ke.c b/src/flash/nor/kinetis_ke.c index 8207504b5..51d5cb504 100644 --- a/src/flash/nor/kinetis_ke.c +++ b/src/flash/nor/kinetis_ke.c @@ -238,19 +238,18 @@ static int kinetis_ke_prepare_flash(struct flash_bank *bank) * Trim internal clock */ switch (KINETIS_KE_SRSID_SUBFAMID(kinfo->sim_srsid)) { + case KINETIS_KE_SRSID_KEX2: + /* Both KE02_20 and KE02_40 should get the same trim value */ + trim_value = 0x4C; + break; - case KINETIS_KE_SRSID_KEX2: - /* Both KE02_20 and KE02_40 should get the same trim value */ - trim_value = 0x4C; - break; + case KINETIS_KE_SRSID_KEX4: + trim_value = 0x54; + break; - case KINETIS_KE_SRSID_KEX4: - trim_value = 0x54; - break; - - case KINETIS_KE_SRSID_KEX6: - trim_value = 0x58; - break; + case KINETIS_KE_SRSID_KEX6: + trim_value = 0x58; + break; } result = target_read_u8(target, ICS_C4, &c4); @@ -293,54 +292,52 @@ static int kinetis_ke_prepare_flash(struct flash_bank *bank) * Configure SIM (bus clock) */ switch (KINETIS_KE_SRSID_SUBFAMID(kinfo->sim_srsid)) { + /* KE02 sub-family operates on SIM_BUSDIV */ + case KINETIS_KE_SRSID_KEX2: + bus_reg_val = 0; + bus_reg_addr = SIM_BUSDIV; + bus_clock = 20000000; + break; - /* KE02 sub-family operates on SIM_BUSDIV */ - case KINETIS_KE_SRSID_KEX2: - bus_reg_val = 0; - bus_reg_addr = SIM_BUSDIV; - bus_clock = 20000000; + /* KE04 and KE06 sub-family operates on SIM_CLKDIV + * Clocks are divided by: + * DIV1 = core clock = 48MHz + * DIV2 = bus clock = 24Mhz + * DIV3 = timer clocks + * So we need to configure SIM_CLKDIV, DIV1 and DIV2 value + */ + case KINETIS_KE_SRSID_KEX4: + /* KE04 devices have the SIM_CLKDIV register at a different offset + * depending on the pin count. */ + switch (KINETIS_KE_SRSID_PINCOUNT(kinfo->sim_srsid)) { + /* 16, 20 and 24 pins */ + case 1: + case 2: + case 3: + bus_reg_addr = SIM_CLKDIV_KE04_16_20_24; break; - /* KE04 and KE06 sub-family operates on SIM_CLKDIV - * Clocks are divided by: - * DIV1 = core clock = 48MHz - * DIV2 = bus clock = 24Mhz - * DIV3 = timer clocks - * So we need to configure SIM_CLKDIV, DIV1 and DIV2 value - */ - case KINETIS_KE_SRSID_KEX4: - /* KE04 devices have the SIM_CLKDIV register at a different offset - * depending on the pin count. */ - switch (KINETIS_KE_SRSID_PINCOUNT(kinfo->sim_srsid)) { - - /* 16, 20 and 24 pins */ - case 1: - case 2: - case 3: - bus_reg_addr = SIM_CLKDIV_KE04_16_20_24; - break; - - /* 44, 64 and 80 pins */ - case 5: - case 7: - case 8: - bus_reg_addr = SIM_CLKDIV_KE04_44_64_80; - break; - - default: - LOG_ERROR("KE04 - Unknown pin count"); - return ERROR_FAIL; - } - - bus_reg_val = SIM_CLKDIV_OUTDIV2_MASK; - bus_clock = 24000000; + /* 44, 64 and 80 pins */ + case 5: + case 7: + case 8: + bus_reg_addr = SIM_CLKDIV_KE04_44_64_80; break; - case KINETIS_KE_SRSID_KEX6: - bus_reg_val = SIM_CLKDIV_OUTDIV2_MASK; - bus_reg_addr = SIM_CLKDIV_KE06; - bus_clock = 24000000; - break; + default: + LOG_ERROR("KE04 - Unknown pin count"); + return ERROR_FAIL; + } + + bus_reg_val = SIM_CLKDIV_OUTDIV2_MASK; + bus_clock = 24000000; + break; + + case KINETIS_KE_SRSID_KEX6: + bus_reg_val = SIM_CLKDIV_OUTDIV2_MASK; + bus_reg_addr = SIM_CLKDIV_KE06; + bus_clock = 24000000; + break; } result = target_write_u32(target, bus_reg_addr, bus_reg_val); @@ -357,20 +354,19 @@ static int kinetis_ke_prepare_flash(struct flash_bank *bank) c2 &= ~ICS_C2_BDIV_MASK; switch (KINETIS_KE_SRSID_SUBFAMID(kinfo->sim_srsid)) { + case KINETIS_KE_SRSID_KEX2: + /* Note: since there are two KE02 types, the KE02_40 @ 40MHz and the + * KE02_20 @ 20MHz, we divide here the ~40MHz ICSFLLCLK down to 20MHz, + * for compatibility. + */ + c2 |= ICS_C2_BDIV(1); + break; - case KINETIS_KE_SRSID_KEX2: - /* Note: since there are two KE02 types, the KE02_40 @ 40MHz and the - * KE02_20 @ 20MHz, we divide here the ~40MHz ICSFLLCLK down to 20MHz, - * for compatibility. - */ - c2 |= ICS_C2_BDIV(1); - break; - - case KINETIS_KE_SRSID_KEX4: - case KINETIS_KE_SRSID_KEX6: - /* For KE04 and KE06, the ICSFLLCLK can be 48MHz. */ - c2 |= ICS_C2_BDIV(0); - break; + case KINETIS_KE_SRSID_KEX4: + case KINETIS_KE_SRSID_KEX6: + /* For KE04 and KE06, the ICSFLLCLK can be 48MHz. */ + c2 |= ICS_C2_BDIV(0); + break; } result = target_write_u8(target, ICS_C2, c2); @@ -1052,21 +1048,21 @@ static int kinetis_ke_probe(struct flash_bank *bank) } switch (KINETIS_KE_SRSID_SUBFAMID(kinfo->sim_srsid)) { - case KINETIS_KE_SRSID_KEX2: - LOG_INFO("KE02 sub-family"); - break; + case KINETIS_KE_SRSID_KEX2: + LOG_INFO("KE02 sub-family"); + break; - case KINETIS_KE_SRSID_KEX4: - LOG_INFO("KE04 sub-family"); - break; + case KINETIS_KE_SRSID_KEX4: + LOG_INFO("KE04 sub-family"); + break; - case KINETIS_KE_SRSID_KEX6: - LOG_INFO("KE06 sub-family"); - break; + case KINETIS_KE_SRSID_KEX6: + LOG_INFO("KE06 sub-family"); + break; - default: - LOG_ERROR("Unsupported KE sub-family"); - return ERROR_FLASH_OPER_UNSUPPORTED; + default: + LOG_ERROR("Unsupported KE sub-family"); + return ERROR_FLASH_OPER_UNSUPPORTED; } /* We can only retrieve the ke0x part, but there is no way to know @@ -1077,41 +1073,40 @@ static int kinetis_ke_probe(struct flash_bank *bank) kinfo->sector_size = 512; switch (KINETIS_KE_SRSID_SUBFAMID(kinfo->sim_srsid)) { + case KINETIS_KE_SRSID_KEX2: + /* Max. 64KB */ + bank->size = 0x00010000; + bank->num_sectors = 128; - case KINETIS_KE_SRSID_KEX2: - /* Max. 64KB */ - bank->size = 0x00010000; - bank->num_sectors = 128; + /* KE02 uses the FTMRH flash controller, + * and registers have a different offset from the + * FTMRE flash controller. Sort this out here. + */ + kinfo->ftmrx_fclkdiv_addr = 0x40020000; + kinfo->ftmrx_fccobix_addr = 0x40020002; + kinfo->ftmrx_fstat_addr = 0x40020006; + kinfo->ftmrx_fprot_addr = 0x40020008; + kinfo->ftmrx_fccobhi_addr = 0x4002000A; + kinfo->ftmrx_fccoblo_addr = 0x4002000B; + break; - /* KE02 uses the FTMRH flash controller, - * and registers have a different offset from the - * FTMRE flash controller. Sort this out here. - */ - kinfo->ftmrx_fclkdiv_addr = 0x40020000; - kinfo->ftmrx_fccobix_addr = 0x40020002; - kinfo->ftmrx_fstat_addr = 0x40020006; - kinfo->ftmrx_fprot_addr = 0x40020008; - kinfo->ftmrx_fccobhi_addr = 0x4002000A; - kinfo->ftmrx_fccoblo_addr = 0x4002000B; - break; + case KINETIS_KE_SRSID_KEX6: + case KINETIS_KE_SRSID_KEX4: + /* Max. 128KB */ + bank->size = 0x00020000; + bank->num_sectors = 256; - case KINETIS_KE_SRSID_KEX6: - case KINETIS_KE_SRSID_KEX4: - /* Max. 128KB */ - bank->size = 0x00020000; - bank->num_sectors = 256; - - /* KE04 and KE06 use the FTMRE flash controller, - * and registers have a different offset from the - * FTMRH flash controller. Sort this out here. - */ - kinfo->ftmrx_fclkdiv_addr = 0x40020003; - kinfo->ftmrx_fccobix_addr = 0x40020001; - kinfo->ftmrx_fstat_addr = 0x40020005; - kinfo->ftmrx_fprot_addr = 0x4002000B; - kinfo->ftmrx_fccobhi_addr = 0x40020009; - kinfo->ftmrx_fccoblo_addr = 0x40020008; - break; + /* KE04 and KE06 use the FTMRE flash controller, + * and registers have a different offset from the + * FTMRH flash controller. Sort this out here. + */ + kinfo->ftmrx_fclkdiv_addr = 0x40020003; + kinfo->ftmrx_fccobix_addr = 0x40020001; + kinfo->ftmrx_fstat_addr = 0x40020005; + kinfo->ftmrx_fprot_addr = 0x4002000B; + kinfo->ftmrx_fccobhi_addr = 0x40020009; + kinfo->ftmrx_fccoblo_addr = 0x40020008; + break; } free(bank->sectors); diff --git a/src/flash/nor/lpc2000.c b/src/flash/nor/lpc2000.c index 09d35f604..1b338ee2e 100644 --- a/src/flash/nor/lpc2000.c +++ b/src/flash/nor/lpc2000.c @@ -383,40 +383,40 @@ static int lpc2000_build_sector_list(struct flash_bank *bank) /* variant 2 has a uniform layout, only number of sectors differs */ switch (bank->size) { - case 4 * 1024: - lpc2000_info->cmd51_max_buffer = 1024; - bank->num_sectors = 1; - break; - case 8 * 1024: - lpc2000_info->cmd51_max_buffer = 1024; - bank->num_sectors = 2; - break; - case 16 * 1024: - bank->num_sectors = 4; - break; - case 32 * 1024: - bank->num_sectors = 8; - break; - case 64 * 1024: - bank->num_sectors = 9; - break; - case 128 * 1024: - bank->num_sectors = 11; - break; - case 256 * 1024: - bank->num_sectors = 15; - break; - case 500 * 1024: - bank->num_sectors = 27; - break; - case 512 * 1024: - case 504 * 1024: - bank->num_sectors = 28; - break; - default: - LOG_ERROR("BUG: unknown bank->size encountered"); - exit(-1); - break; + case 4 * 1024: + lpc2000_info->cmd51_max_buffer = 1024; + bank->num_sectors = 1; + break; + case 8 * 1024: + lpc2000_info->cmd51_max_buffer = 1024; + bank->num_sectors = 2; + break; + case 16 * 1024: + bank->num_sectors = 4; + break; + case 32 * 1024: + bank->num_sectors = 8; + break; + case 64 * 1024: + bank->num_sectors = 9; + break; + case 128 * 1024: + bank->num_sectors = 11; + break; + case 256 * 1024: + bank->num_sectors = 15; + break; + case 500 * 1024: + bank->num_sectors = 27; + break; + case 512 * 1024: + case 504 * 1024: + bank->num_sectors = 28; + break; + default: + LOG_ERROR("BUG: unknown bank->size encountered"); + exit(-1); + break; } bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors); @@ -448,37 +448,37 @@ static int lpc2000_build_sector_list(struct flash_bank *bank) lpc2000_info->iap_max_stack = 128; switch (bank->size) { - case 4 * 1024: - lpc2000_info->cmd51_max_buffer = 256; - bank->num_sectors = 1; - break; - case 8 * 1024: - lpc2000_info->cmd51_max_buffer = 512; - bank->num_sectors = 2; - break; - case 16 * 1024: - lpc2000_info->cmd51_max_buffer = 512; - bank->num_sectors = 4; - break; - case 32 * 1024: - lpc2000_info->cmd51_max_buffer = 1024; - bank->num_sectors = 8; - break; - case 64 * 1024: - bank->num_sectors = 16; - break; - case 128 * 1024: - bank->num_sectors = 18; + case 4 * 1024: + lpc2000_info->cmd51_max_buffer = 256; + bank->num_sectors = 1; break; - case 256 * 1024: - bank->num_sectors = 22; - break; - case 512 * 1024: - bank->num_sectors = 30; - break; - default: - LOG_ERROR("BUG: unknown bank->size encountered"); - exit(-1); + case 8 * 1024: + lpc2000_info->cmd51_max_buffer = 512; + bank->num_sectors = 2; + break; + case 16 * 1024: + lpc2000_info->cmd51_max_buffer = 512; + bank->num_sectors = 4; + break; + case 32 * 1024: + lpc2000_info->cmd51_max_buffer = 1024; + bank->num_sectors = 8; + break; + case 64 * 1024: + bank->num_sectors = 16; + break; + case 128 * 1024: + bank->num_sectors = 18; + break; + case 256 * 1024: + bank->num_sectors = 22; + break; + case 512 * 1024: + bank->num_sectors = 30; + break; + default: + LOG_ERROR("BUG: unknown bank->size encountered"); + exit(-1); } bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors); @@ -497,18 +497,18 @@ static int lpc2000_build_sector_list(struct flash_bank *bank) lpc2000_info->iap_max_stack = 208; switch (bank->size) { - case 256 * 1024: - bank->num_sectors = 11; - break; - case 384 * 1024: - bank->num_sectors = 13; - break; - case 512 * 1024: - bank->num_sectors = 15; - break; - default: - LOG_ERROR("BUG: unknown bank->size encountered"); - exit(-1); + case 256 * 1024: + bank->num_sectors = 11; + break; + case 384 * 1024: + bank->num_sectors = 13; + break; + case 512 * 1024: + bank->num_sectors = 15; + break; + default: + LOG_ERROR("BUG: unknown bank->size encountered"); + exit(-1); } bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors); @@ -529,30 +529,30 @@ static int lpc2000_build_sector_list(struct flash_bank *bank) lpc2000_info->cmd51_max_buffer = 256; /* smallest MCU in the series, LPC810, has 1 kB of SRAM */ switch (bank->size) { - case 4 * 1024: - bank->num_sectors = 4; - break; - case 8 * 1024: - bank->num_sectors = 8; - break; - case 16 * 1024: - bank->num_sectors = 16; - break; - case 30 * 1024: - lpc2000_info->cmd51_max_buffer = 1024; /* For LPC8N04 and NHS31xx, have 8kB of SRAM */ - bank->num_sectors = 30; /* There have only 30kB of writable Flash out of 32kB */ - break; - case 32 * 1024: - lpc2000_info->cmd51_max_buffer = 1024; /* For LPC824, has 8kB of SRAM */ - bank->num_sectors = 32; - break; - case 64 * 1024: - lpc2000_info->cmd51_max_buffer = 1024; /* For LPC844, has 8kB of SRAM */ - bank->num_sectors = 64; - break; - default: - LOG_ERROR("BUG: unknown bank->size encountered"); - exit(-1); + case 4 * 1024: + bank->num_sectors = 4; + break; + case 8 * 1024: + bank->num_sectors = 8; + break; + case 16 * 1024: + bank->num_sectors = 16; + break; + case 30 * 1024: + lpc2000_info->cmd51_max_buffer = 1024; /* For LPC8N04 and NHS31xx, have 8kB of SRAM */ + bank->num_sectors = 30; /* There have only 30kB of writable Flash out of 32kB */ + break; + case 32 * 1024: + lpc2000_info->cmd51_max_buffer = 1024; /* For LPC824, has 8kB of SRAM */ + bank->num_sectors = 32; + break; + case 64 * 1024: + lpc2000_info->cmd51_max_buffer = 1024; /* For LPC844, has 8kB of SRAM */ + bank->num_sectors = 64; + break; + default: + LOG_ERROR("BUG: unknown bank->size encountered"); + exit(-1); } bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors); @@ -602,18 +602,18 @@ static int lpc2000_build_sector_list(struct flash_bank *bank) lpc2000_info->iap_max_stack = 128; switch (bank->size) { - case 64 * 1024: - bank->num_sectors = 16; - break; - case 128 * 1024: - bank->num_sectors = 32; - break; - case 256 * 1024: - bank->num_sectors = 64; - break; - default: - LOG_ERROR("BUG: unknown bank->size encountered"); - exit(-1); + case 64 * 1024: + bank->num_sectors = 16; + break; + case 128 * 1024: + bank->num_sectors = 32; + break; + case 256 * 1024: + bank->num_sectors = 64; + break; + default: + LOG_ERROR("BUG: unknown bank->size encountered"); + exit(-1); } bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors); @@ -633,15 +633,15 @@ static int lpc2000_build_sector_list(struct flash_bank *bank) lpc2000_info->iap_max_stack = 128; switch (bank->size) { - case 256 * 1024: - bank->num_sectors = 8; - break; - case 512 * 1024: - bank->num_sectors = 16; - break; - default: - LOG_ERROR("BUG: unknown bank->size encountered"); - exit(-1); + case 256 * 1024: + bank->num_sectors = 8; + break; + case 512 * 1024: + bank->num_sectors = 16; + break; + default: + LOG_ERROR("BUG: unknown bank->size encountered"); + exit(-1); } bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors); @@ -686,24 +686,24 @@ static int lpc2000_iap_working_area_init(struct flash_bank *bank, struct working /* write IAP code to working area */ switch (lpc2000_info->variant) { - case LPC800: - case LPC1100: - case LPC1500: - case LPC1700: - case LPC4300: - case LPC54100: - case LPC_AUTO: - target_buffer_set_u32(target, jump_gate, ARMV4_5_T_BX(12)); - target_buffer_set_u32(target, jump_gate + 4, ARMV5_T_BKPT(0)); - break; - case LPC2000_V1: - case LPC2000_V2: - target_buffer_set_u32(target, jump_gate, ARMV4_5_BX(12)); - target_buffer_set_u32(target, jump_gate + 4, ARMV4_5_B(0xfffffe, 0)); - break; - default: - LOG_ERROR("BUG: unknown lpc2000_info->variant encountered"); - exit(-1); + case LPC800: + case LPC1100: + case LPC1500: + case LPC1700: + case LPC4300: + case LPC54100: + case LPC_AUTO: + target_buffer_set_u32(target, jump_gate, ARMV4_5_T_BX(12)); + target_buffer_set_u32(target, jump_gate + 4, ARMV5_T_BKPT(0)); + break; + case LPC2000_V1: + case LPC2000_V2: + target_buffer_set_u32(target, jump_gate, ARMV4_5_BX(12)); + target_buffer_set_u32(target, jump_gate + 4, ARMV4_5_B(0xfffffe, 0)); + break; + default: + LOG_ERROR("BUG: unknown lpc2000_info->variant encountered"); + exit(-1); } int retval = target_write_memory(target, (*iap_working_area)->address, 4, 2, jump_gate); @@ -729,36 +729,36 @@ static int lpc2000_iap_call(struct flash_bank *bank, struct working_area *iap_wo uint32_t iap_entry_point = 0; /* to make compiler happier */ switch (lpc2000_info->variant) { - case LPC800: - case LPC1100: - case LPC1700: - case LPC_AUTO: - armv7m_info.common_magic = ARMV7M_COMMON_MAGIC; - armv7m_info.core_mode = ARM_MODE_THREAD; - iap_entry_point = 0x1fff1ff1; - break; - case LPC1500: - case LPC54100: - armv7m_info.common_magic = ARMV7M_COMMON_MAGIC; - armv7m_info.core_mode = ARM_MODE_THREAD; - iap_entry_point = 0x03000205; - break; - case LPC2000_V1: - case LPC2000_V2: - arm_algo.common_magic = ARM_COMMON_MAGIC; - arm_algo.core_mode = ARM_MODE_SVC; - arm_algo.core_state = ARM_STATE_ARM; - iap_entry_point = 0x7ffffff1; - break; - case LPC4300: - armv7m_info.common_magic = ARMV7M_COMMON_MAGIC; - armv7m_info.core_mode = ARM_MODE_THREAD; - /* read out IAP entry point from ROM driver table at 0x10400100 */ - target_read_u32(target, 0x10400100, &iap_entry_point); - break; - default: - LOG_ERROR("BUG: unknown lpc2000->variant encountered"); - exit(-1); + case LPC800: + case LPC1100: + case LPC1700: + case LPC_AUTO: + armv7m_info.common_magic = ARMV7M_COMMON_MAGIC; + armv7m_info.core_mode = ARM_MODE_THREAD; + iap_entry_point = 0x1fff1ff1; + break; + case LPC1500: + case LPC54100: + armv7m_info.common_magic = ARMV7M_COMMON_MAGIC; + armv7m_info.core_mode = ARM_MODE_THREAD; + iap_entry_point = 0x03000205; + break; + case LPC2000_V1: + case LPC2000_V2: + arm_algo.common_magic = ARM_COMMON_MAGIC; + arm_algo.core_mode = ARM_MODE_SVC; + arm_algo.core_state = ARM_STATE_ARM; + iap_entry_point = 0x7ffffff1; + break; + case LPC4300: + armv7m_info.common_magic = ARMV7M_COMMON_MAGIC; + armv7m_info.core_mode = ARM_MODE_THREAD; + /* read out IAP entry point from ROM driver table at 0x10400100 */ + target_read_u32(target, 0x10400100, &iap_entry_point); + break; + default: + LOG_ERROR("BUG: unknown lpc2000->variant encountered"); + exit(-1); } if (lpc2000_info->iap_entry_alternative != 0x0) @@ -791,43 +791,43 @@ static int lpc2000_iap_call(struct flash_bank *bank, struct working_area *iap_wo buf_set_u32(reg_params[2].value, 0, 32, iap_entry_point); switch (lpc2000_info->variant) { - case LPC800: - case LPC1100: - case LPC1500: - case LPC1700: - case LPC4300: - case LPC54100: - case LPC_AUTO: - /* IAP stack */ - init_reg_param(®_params[3], "sp", 32, PARAM_OUT); - buf_set_u32(reg_params[3].value, 0, 32, - iap_working_area->address + IAP_CODE_LEN + lpc2000_info->iap_max_stack); + case LPC800: + case LPC1100: + case LPC1500: + case LPC1700: + case LPC4300: + case LPC54100: + case LPC_AUTO: + /* IAP stack */ + init_reg_param(®_params[3], "sp", 32, PARAM_OUT); + buf_set_u32(reg_params[3].value, 0, 32, + iap_working_area->address + IAP_CODE_LEN + lpc2000_info->iap_max_stack); - /* return address */ - init_reg_param(®_params[4], "lr", 32, PARAM_OUT); - buf_set_u32(reg_params[4].value, 0, 32, (iap_working_area->address + 0x04) | 1); - /* bit0 of LR = 1 to return in Thumb mode */ + /* return address */ + init_reg_param(®_params[4], "lr", 32, PARAM_OUT); + buf_set_u32(reg_params[4].value, 0, 32, (iap_working_area->address + 0x04) | 1); + /* bit0 of LR = 1 to return in Thumb mode */ - target_run_algorithm(target, 2, mem_params, 5, reg_params, iap_working_area->address, 0, 10000, - &armv7m_info); - break; - case LPC2000_V1: - case LPC2000_V2: - /* IAP stack */ - init_reg_param(®_params[3], "sp_svc", 32, PARAM_OUT); - buf_set_u32(reg_params[3].value, 0, 32, - iap_working_area->address + IAP_CODE_LEN + lpc2000_info->iap_max_stack); + target_run_algorithm(target, 2, mem_params, 5, reg_params, iap_working_area->address, 0, 10000, + &armv7m_info); + break; + case LPC2000_V1: + case LPC2000_V2: + /* IAP stack */ + init_reg_param(®_params[3], "sp_svc", 32, PARAM_OUT); + buf_set_u32(reg_params[3].value, 0, 32, + iap_working_area->address + IAP_CODE_LEN + lpc2000_info->iap_max_stack); - /* return address */ - init_reg_param(®_params[4], "lr_svc", 32, PARAM_OUT); - buf_set_u32(reg_params[4].value, 0, 32, iap_working_area->address + 0x04); + /* return address */ + init_reg_param(®_params[4], "lr_svc", 32, PARAM_OUT); + buf_set_u32(reg_params[4].value, 0, 32, iap_working_area->address + 0x04); - target_run_algorithm(target, 2, mem_params, 5, reg_params, iap_working_area->address, - iap_working_area->address + 0x4, 10000, &arm_algo); - break; - default: - LOG_ERROR("BUG: unknown lpc2000->variant encountered"); - exit(-1); + target_run_algorithm(target, 2, mem_params, 5, reg_params, iap_working_area->address, + iap_working_area->address + 0x4, 10000, &arm_algo); + break; + default: + LOG_ERROR("BUG: unknown lpc2000->variant encountered"); + exit(-1); } int status_code = target_buffer_get_u32(target, mem_params[1].value); @@ -877,24 +877,24 @@ static int lpc2000_iap_blank_check(struct flash_bank *bank, unsigned int first, int status_code = lpc2000_iap_call(bank, iap_working_area, 53, param_table, result_table); switch (status_code) { - case ERROR_FLASH_OPERATION_FAILED: - retval = ERROR_FLASH_OPERATION_FAILED; - break; - case LPC2000_CMD_SUCCESS: - bank->sectors[i].is_erased = 1; - break; - case LPC2000_SECTOR_NOT_BLANK: - bank->sectors[i].is_erased = 0; - break; - case LPC2000_INVALID_SECTOR: - bank->sectors[i].is_erased = 0; - break; - case LPC2000_BUSY: - retval = ERROR_FLASH_BUSY; - break; - default: - LOG_ERROR("BUG: unknown LPC2000 status code %i", status_code); - exit(-1); + case ERROR_FLASH_OPERATION_FAILED: + retval = ERROR_FLASH_OPERATION_FAILED; + break; + case LPC2000_CMD_SUCCESS: + bank->sectors[i].is_erased = 1; + break; + case LPC2000_SECTOR_NOT_BLANK: + bank->sectors[i].is_erased = 0; + break; + case LPC2000_INVALID_SECTOR: + bank->sectors[i].is_erased = 0; + break; + case LPC2000_BUSY: + retval = ERROR_FLASH_BUSY; + break; + default: + LOG_ERROR("BUG: unknown LPC2000 status code %i", status_code); + exit(-1); } } @@ -1002,18 +1002,18 @@ static int lpc2000_erase(struct flash_bank *bank, unsigned int first, /* Prepare sectors */ int status_code = lpc2000_iap_call(bank, iap_working_area, 50, param_table, result_table); switch (status_code) { - case ERROR_FLASH_OPERATION_FAILED: - retval = ERROR_FLASH_OPERATION_FAILED; - break; - case LPC2000_CMD_SUCCESS: - break; - case LPC2000_INVALID_SECTOR: - retval = ERROR_FLASH_SECTOR_INVALID; - break; - default: - LOG_WARNING("lpc2000 prepare sectors returned %i", status_code); - retval = ERROR_FLASH_OPERATION_FAILED; - break; + case ERROR_FLASH_OPERATION_FAILED: + retval = ERROR_FLASH_OPERATION_FAILED; + break; + case LPC2000_CMD_SUCCESS: + break; + case LPC2000_INVALID_SECTOR: + retval = ERROR_FLASH_SECTOR_INVALID; + break; + default: + LOG_WARNING("lpc2000 prepare sectors returned %i", status_code); + retval = ERROR_FLASH_OPERATION_FAILED; + break; } if (retval == ERROR_OK) { @@ -1024,18 +1024,18 @@ static int lpc2000_erase(struct flash_bank *bank, unsigned int first, status_code = lpc2000_iap_call(bank, iap_working_area, 52, param_table, result_table); switch (status_code) { - case ERROR_FLASH_OPERATION_FAILED: - retval = ERROR_FLASH_OPERATION_FAILED; - break; - case LPC2000_CMD_SUCCESS: - break; - case LPC2000_INVALID_SECTOR: - retval = ERROR_FLASH_SECTOR_INVALID; - break; - default: - LOG_WARNING("lpc2000 erase sectors returned %i", status_code); - retval = ERROR_FLASH_OPERATION_FAILED; - break; + case ERROR_FLASH_OPERATION_FAILED: + retval = ERROR_FLASH_OPERATION_FAILED; + break; + case LPC2000_CMD_SUCCESS: + break; + case LPC2000_INVALID_SECTOR: + retval = ERROR_FLASH_SECTOR_INVALID; + break; + default: + LOG_WARNING("lpc2000 erase sectors returned %i", status_code); + retval = ERROR_FLASH_OPERATION_FAILED; + break; } } @@ -1145,18 +1145,18 @@ static int lpc2000_write(struct flash_bank *bank, const uint8_t *buffer, uint32_ int status_code = lpc2000_iap_call(bank, iap_working_area, 50, param_table, result_table); switch (status_code) { - case ERROR_FLASH_OPERATION_FAILED: - retval = ERROR_FLASH_OPERATION_FAILED; - break; - case LPC2000_CMD_SUCCESS: - break; - case LPC2000_INVALID_SECTOR: - retval = ERROR_FLASH_SECTOR_INVALID; - break; - default: - LOG_WARNING("lpc2000 prepare sectors returned %i", status_code); - retval = ERROR_FLASH_OPERATION_FAILED; - break; + case ERROR_FLASH_OPERATION_FAILED: + retval = ERROR_FLASH_OPERATION_FAILED; + break; + case LPC2000_CMD_SUCCESS: + break; + case LPC2000_INVALID_SECTOR: + retval = ERROR_FLASH_SECTOR_INVALID; + break; + default: + LOG_WARNING("lpc2000 prepare sectors returned %i", status_code); + retval = ERROR_FLASH_OPERATION_FAILED; + break; } /* Exit if error occurred */ @@ -1187,18 +1187,18 @@ static int lpc2000_write(struct flash_bank *bank, const uint8_t *buffer, uint32_ param_table[3] = lpc2000_info->cclk; status_code = lpc2000_iap_call(bank, iap_working_area, 51, param_table, result_table); switch (status_code) { - case ERROR_FLASH_OPERATION_FAILED: - retval = ERROR_FLASH_OPERATION_FAILED; - break; - case LPC2000_CMD_SUCCESS: - break; - case LPC2000_INVALID_SECTOR: - retval = ERROR_FLASH_SECTOR_INVALID; - break; - default: - LOG_WARNING("lpc2000 returned %i", status_code); - retval = ERROR_FLASH_OPERATION_FAILED; - break; + case ERROR_FLASH_OPERATION_FAILED: + retval = ERROR_FLASH_OPERATION_FAILED; + break; + case LPC2000_CMD_SUCCESS: + break; + case LPC2000_INVALID_SECTOR: + retval = ERROR_FLASH_SECTOR_INVALID; + break; + default: + LOG_WARNING("lpc2000 returned %i", status_code); + retval = ERROR_FLASH_OPERATION_FAILED; + break; } /* Exit if error occurred */ @@ -1267,240 +1267,240 @@ static int lpc2000_auto_probe_flash(struct flash_bank *bank) } switch (part_id) { - case LPC1110_1: - case LPC1110_2: - lpc2000_info->variant = LPC1100; - bank->size = 4 * 1024; - break; + case LPC1110_1: + case LPC1110_2: + lpc2000_info->variant = LPC1100; + bank->size = 4 * 1024; + break; - case LPC1111_002_1: - case LPC1111_002_2: - case LPC1111_101_1: - case LPC1111_101_2: - case LPC1111_103_1: - case LPC1111_201_1: - case LPC1111_201_2: - case LPC1111_203_1: - case LPC11A11_001_1: - case LPC11E11_101: - case LPC1311: - case LPC1311_1: - lpc2000_info->variant = LPC1100; - bank->size = 8 * 1024; - break; + case LPC1111_002_1: + case LPC1111_002_2: + case LPC1111_101_1: + case LPC1111_101_2: + case LPC1111_103_1: + case LPC1111_201_1: + case LPC1111_201_2: + case LPC1111_203_1: + case LPC11A11_001_1: + case LPC11E11_101: + case LPC1311: + case LPC1311_1: + lpc2000_info->variant = LPC1100; + bank->size = 8 * 1024; + break; - case LPC1112_101_1: - case LPC1112_101_2: - case LPC1112_102_1: - case LPC1112_102_2: - case LPC1112_103_1: - case LPC1112_201_1: - case LPC1112_201_2: - case LPC1112_203_1: - case LPC11A02_1: - case LPC11C12_301_1: - case LPC11C22_301_1: - case LPC11A12_101_1: - case LPC11E12_201: - case LPC11U12_201_1: - case LPC11U12_201_2: - case LPC1342: - lpc2000_info->variant = LPC1100; - bank->size = 16 * 1024; - break; + case LPC1112_101_1: + case LPC1112_101_2: + case LPC1112_102_1: + case LPC1112_102_2: + case LPC1112_103_1: + case LPC1112_201_1: + case LPC1112_201_2: + case LPC1112_203_1: + case LPC11A02_1: + case LPC11C12_301_1: + case LPC11C22_301_1: + case LPC11A12_101_1: + case LPC11E12_201: + case LPC11U12_201_1: + case LPC11U12_201_2: + case LPC1342: + lpc2000_info->variant = LPC1100; + bank->size = 16 * 1024; + break; - case LPC1113_201_1: - case LPC1113_201_2: - case LPC1113_203_1: - case LPC1113_301_1: - case LPC1113_301_2: - case LPC1113_303_1: - case LPC11A13_201_1: - case LPC11E13_301: - case LPC11U13_201_1: - case LPC11U13_201_2: - case LPC11U23_301: - lpc2000_info->variant = LPC1100; - bank->size = 24 * 1024; - break; + case LPC1113_201_1: + case LPC1113_201_2: + case LPC1113_203_1: + case LPC1113_301_1: + case LPC1113_301_2: + case LPC1113_303_1: + case LPC11A13_201_1: + case LPC11E13_301: + case LPC11U13_201_1: + case LPC11U13_201_2: + case LPC11U23_301: + lpc2000_info->variant = LPC1100; + bank->size = 24 * 1024; + break; - case LPC1114_102_1: - case LPC1114_102_2: - case LPC1114_201_1: - case LPC1114_201_2: - case LPC1114_203_1: - case LPC1114_301_1: - case LPC1114_301_2: - case LPC1114_303_1: - case LPC11A04_1: - case LPC11A14_301_1: - case LPC11A14_301_2: - case LPC11C14_301_1: - case LPC11C24_301_1: - case LPC11E14_401: - case LPC11U14_201_1: - case LPC11U14_201_2: - case LPC11U24_301: - case LPC11U24_401: - case LPC1313: - case LPC1313_1: - case LPC1315: - case LPC1343: - case LPC1343_1: - case LPC1345: - lpc2000_info->variant = LPC1100; - bank->size = 32 * 1024; - break; + case LPC1114_102_1: + case LPC1114_102_2: + case LPC1114_201_1: + case LPC1114_201_2: + case LPC1114_203_1: + case LPC1114_301_1: + case LPC1114_301_2: + case LPC1114_303_1: + case LPC11A04_1: + case LPC11A14_301_1: + case LPC11A14_301_2: + case LPC11C14_301_1: + case LPC11C24_301_1: + case LPC11E14_401: + case LPC11U14_201_1: + case LPC11U14_201_2: + case LPC11U24_301: + case LPC11U24_401: + case LPC1313: + case LPC1313_1: + case LPC1315: + case LPC1343: + case LPC1343_1: + case LPC1345: + lpc2000_info->variant = LPC1100; + bank->size = 32 * 1024; + break; - case LPC1751_1: - case LPC1751_2: - lpc2000_info->variant = LPC1700; - bank->size = 32 * 1024; - break; + case LPC1751_1: + case LPC1751_2: + lpc2000_info->variant = LPC1700; + bank->size = 32 * 1024; + break; - case LPC11U34_311: - lpc2000_info->variant = LPC1100; - bank->size = 40 * 1024; - break; + case LPC11U34_311: + lpc2000_info->variant = LPC1100; + bank->size = 40 * 1024; + break; - case LPC1114_323_1: - case LPC11U34_421: - case LPC1316: - case LPC1346: - lpc2000_info->variant = LPC1100; - bank->size = 48 * 1024; - break; + case LPC1114_323_1: + case LPC11U34_421: + case LPC1316: + case LPC1346: + lpc2000_info->variant = LPC1100; + bank->size = 48 * 1024; + break; - case LPC1114_333_1: - lpc2000_info->variant = LPC1100; - bank->size = 56 * 1024; - break; + case LPC1114_333_1: + lpc2000_info->variant = LPC1100; + bank->size = 56 * 1024; + break; - case LPC1115_303_1: - case LPC11U35_401: - case LPC11U35_501: - case LPC11E66: - case LPC11U66: - case LPC1317: - case LPC1347: - lpc2000_info->variant = LPC1100; - bank->size = 64 * 1024; - break; + case LPC1115_303_1: + case LPC11U35_401: + case LPC11U35_501: + case LPC11E66: + case LPC11U66: + case LPC1317: + case LPC1347: + lpc2000_info->variant = LPC1100; + bank->size = 64 * 1024; + break; - case LPC1752: - case LPC4072: - lpc2000_info->variant = LPC1700; - bank->size = 64 * 1024; - break; + case LPC1752: + case LPC4072: + lpc2000_info->variant = LPC1700; + bank->size = 64 * 1024; + break; - case LPC11E36_501: - case LPC11U36_401: - lpc2000_info->variant = LPC1100; - bank->size = 96 * 1024; - break; + case LPC11E36_501: + case LPC11U36_401: + lpc2000_info->variant = LPC1100; + bank->size = 96 * 1024; + break; - case LPC11E37_401: - case LPC11E37_501: - case LPC11U37_401: - case LPC11U37H_401: - case LPC11U37_501: - case LPC11E67: - case LPC11E68: - case LPC11U67_1: - case LPC11U67_2: - lpc2000_info->variant = LPC1100; - bank->size = 128 * 1024; - break; + case LPC11E37_401: + case LPC11E37_501: + case LPC11U37_401: + case LPC11U37H_401: + case LPC11U37_501: + case LPC11E67: + case LPC11E68: + case LPC11U67_1: + case LPC11U67_2: + lpc2000_info->variant = LPC1100; + bank->size = 128 * 1024; + break; - case LPC1754: - case LPC1764: - case LPC1774: - case LPC4074: - lpc2000_info->variant = LPC1700; - bank->size = 128 * 1024; - break; + case LPC1754: + case LPC1764: + case LPC1774: + case LPC4074: + lpc2000_info->variant = LPC1700; + bank->size = 128 * 1024; + break; - case LPC11U68_1: - case LPC11U68_2: - lpc2000_info->variant = LPC1100; - bank->size = 256 * 1024; - break; + case LPC11U68_1: + case LPC11U68_2: + lpc2000_info->variant = LPC1100; + bank->size = 256 * 1024; + break; - case LPC1756: - case LPC1763: - case LPC1765: - case LPC1766: - case LPC1776: - case LPC1785: - case LPC1786: - case LPC4076: - lpc2000_info->variant = LPC1700; - bank->size = 256 * 1024; - break; + case LPC1756: + case LPC1763: + case LPC1765: + case LPC1766: + case LPC1776: + case LPC1785: + case LPC1786: + case LPC4076: + lpc2000_info->variant = LPC1700; + bank->size = 256 * 1024; + break; - case LPC1758: - case LPC1759: - case LPC1767: - case LPC1768: - case LPC1769: - case LPC1777: - case LPC1778: - case LPC1787: - case LPC1788: - case LPC4078: - case LPC4088: - lpc2000_info->variant = LPC1700; - bank->size = 512 * 1024; - break; + case LPC1758: + case LPC1759: + case LPC1767: + case LPC1768: + case LPC1769: + case LPC1777: + case LPC1778: + case LPC1787: + case LPC1788: + case LPC4078: + case LPC4088: + lpc2000_info->variant = LPC1700; + bank->size = 512 * 1024; + break; - case LPC810_021: - lpc2000_info->variant = LPC800; - bank->size = 4 * 1024; - break; + case LPC810_021: + lpc2000_info->variant = LPC800; + bank->size = 4 * 1024; + break; - case LPC811_001: - lpc2000_info->variant = LPC800; - bank->size = 8 * 1024; - break; + case LPC811_001: + lpc2000_info->variant = LPC800; + bank->size = 8 * 1024; + break; - case LPC812_101: - case LPC812_101_1: - case LPC812_101_2: - case LPC812_101_3: - case LPC822_101: - case LPC822_101_1: - lpc2000_info->variant = LPC800; - bank->size = 16 * 1024; - break; + case LPC812_101: + case LPC812_101_1: + case LPC812_101_2: + case LPC812_101_3: + case LPC822_101: + case LPC822_101_1: + lpc2000_info->variant = LPC800; + bank->size = 16 * 1024; + break; - case LPC824_201: - case LPC824_201_1: - lpc2000_info->variant = LPC800; - bank->size = 32 * 1024; - break; + case LPC824_201: + case LPC824_201_1: + lpc2000_info->variant = LPC800; + bank->size = 32 * 1024; + break; - case LPC8N04: - case NHS3100: - case NHS3152: - case NHS3153: - lpc2000_info->variant = LPC800; - bank->size = 30 * 1024; - break; + case LPC8N04: + case NHS3100: + case NHS3152: + case NHS3153: + lpc2000_info->variant = LPC800; + bank->size = 30 * 1024; + break; - case LPC844_201: - case LPC844_201_1: - case LPC844_201_2: - case LPC845_301: - case LPC845_301_1: - case LPC845_301_2: - case LPC845_301_3: - lpc2000_info->variant = LPC800; - bank->size = 64 * 1024; - break; + case LPC844_201: + case LPC844_201_1: + case LPC844_201_2: + case LPC845_301: + case LPC845_301_1: + case LPC845_301_2: + case LPC845_301_3: + lpc2000_info->variant = LPC800; + bank->size = 64 * 1024; + break; - default: - LOG_ERROR("BUG: unknown Part ID encountered: 0x%" PRIx32, part_id); - exit(-1); + default: + LOG_ERROR("BUG: unknown Part ID encountered: 0x%" PRIx32, part_id); + exit(-1); } return ERROR_OK; diff --git a/src/flash/nor/msp432.c b/src/flash/nor/msp432.c index e79841b47..d7cc253ae 100644 --- a/src/flash/nor/msp432.c +++ b/src/flash/nor/msp432.c @@ -90,56 +90,56 @@ static int msp432_device_type(uint32_t family_type, uint32_t device_id, /* Examine the device ID and hardware revision to get the device type */ switch (device_id) { - case 0xA000: - case 0xA001: - case 0xA002: - case 0xA003: - case 0xA004: - case 0xA005: - /* Device is definitely MSP432P401x, check hardware revision */ - if (hardware_rev == 0x41 || hardware_rev == 0x42) { - /* Rev A or B of the silicon has been deprecated */ - device_type = MSP432P401X_DEPR; - } else if (hardware_rev >= 0x43 && hardware_rev <= 0x49) { - /* Current and future revisions of the MSP432P401x device */ - device_type = MSP432P401X; - } else { - /* Unknown or unanticipated hardware revision */ - device_type = MSP432P401X_GUESS; - } - break; - case 0xA010: - case 0xA012: - case 0xA016: - case 0xA019: - case 0xA01F: - case 0xA020: - case 0xA022: - case 0xA026: - case 0xA029: - case 0xA02F: - /* Device is definitely MSP432P411x, check hardware revision */ - if (hardware_rev >= 0x41 && hardware_rev <= 0x49) { - /* Current and future revisions of the MSP432P411x device */ - device_type = MSP432P411X; - } else { - /* Unknown or unanticipated hardware revision */ - device_type = MSP432P411X_GUESS; - } - break; - case 0xFFFF: - /* Device is very early silicon that has been deprecated */ + case 0xA000: + case 0xA001: + case 0xA002: + case 0xA003: + case 0xA004: + case 0xA005: + /* Device is definitely MSP432P401x, check hardware revision */ + if (hardware_rev == 0x41 || hardware_rev == 0x42) { + /* Rev A or B of the silicon has been deprecated */ device_type = MSP432P401X_DEPR; - break; - default: - if (device_id < 0xA010) { - /* Wild guess that this is an MSP432P401x */ - device_type = MSP432P401X_GUESS; - } else { - /* Reasonable guess that this is a new variant */ - device_type = MSP432P411X_GUESS; - } - break; + } else if (hardware_rev >= 0x43 && hardware_rev <= 0x49) { + /* Current and future revisions of the MSP432P401x device */ + device_type = MSP432P401X; + } else { + /* Unknown or unanticipated hardware revision */ + device_type = MSP432P401X_GUESS; + } + break; + case 0xA010: + case 0xA012: + case 0xA016: + case 0xA019: + case 0xA01F: + case 0xA020: + case 0xA022: + case 0xA026: + case 0xA029: + case 0xA02F: + /* Device is definitely MSP432P411x, check hardware revision */ + if (hardware_rev >= 0x41 && hardware_rev <= 0x49) { + /* Current and future revisions of the MSP432P411x device */ + device_type = MSP432P411X; + } else { + /* Unknown or unanticipated hardware revision */ + device_type = MSP432P411X_GUESS; + } + break; + case 0xFFFF: + /* Device is very early silicon that has been deprecated */ + device_type = MSP432P401X_DEPR; + break; + default: + if (device_id < 0xA010) { + /* Wild guess that this is an MSP432P401x */ + device_type = MSP432P401X_GUESS; + } else { + /* Reasonable guess that this is a new variant */ + device_type = MSP432P411X_GUESS; + } + break; } } @@ -149,22 +149,22 @@ static int msp432_device_type(uint32_t family_type, uint32_t device_id, static const char *msp432_return_text(uint32_t return_code) { switch (return_code) { - case FLASH_BUSY: - return "FLASH_BUSY"; - case FLASH_SUCCESS: - return "FLASH_SUCCESS"; - case FLASH_ERROR: - return "FLASH_ERROR"; - case FLASH_TIMEOUT_ERROR: - return "FLASH_TIMEOUT_ERROR"; - case FLASH_VERIFY_ERROR: - return "FLASH_VERIFY_WRONG"; - case FLASH_WRONG_COMMAND: - return "FLASH_WRONG_COMMAND"; - case FLASH_POWER_ERROR: - return "FLASH_POWER_ERROR"; - default: - return "UNDEFINED_RETURN_CODE"; + case FLASH_BUSY: + return "FLASH_BUSY"; + case FLASH_SUCCESS: + return "FLASH_SUCCESS"; + case FLASH_ERROR: + return "FLASH_ERROR"; + case FLASH_TIMEOUT_ERROR: + return "FLASH_TIMEOUT_ERROR"; + case FLASH_VERIFY_ERROR: + return "FLASH_VERIFY_WRONG"; + case FLASH_WRONG_COMMAND: + return "FLASH_WRONG_COMMAND"; + case FLASH_POWER_ERROR: + return "FLASH_POWER_ERROR"; + default: + return "UNDEFINED_RETURN_CODE"; } } @@ -244,14 +244,14 @@ static int msp432_wait_inactive(struct target *target, uint32_t buffer) int retval; switch (buffer) { - case 1: /* Buffer 1 */ - status_addr = ALGO_BUFFER1_STATUS_ADDR; - break; - case 2: /* Buffer 2 */ - status_addr = ALGO_BUFFER2_STATUS_ADDR; - break; - default: - return ERROR_FAIL; + case 1: /* Buffer 1 */ + status_addr = ALGO_BUFFER1_STATUS_ADDR; + break; + case 2: /* Buffer 2 */ + status_addr = ALGO_BUFFER2_STATUS_ADDR; + break; + default: + return ERROR_FAIL; } start_ms = timeval_ms(); @@ -295,27 +295,27 @@ static int msp432_init(struct flash_bank *bank) /* Choose appropriate flash helper algorithm */ switch (msp432_bank->device_type) { - case MSP432P401X: - case MSP432P401X_DEPR: - case MSP432P401X_GUESS: - default: - loader_code = msp432p401x_algo; - loader_size = sizeof(msp432p401x_algo); - algo_entry_addr = P4_ALGO_ENTRY_ADDR; - break; - case MSP432P411X: - case MSP432P411X_GUESS: - loader_code = msp432p411x_algo; - loader_size = sizeof(msp432p411x_algo); - algo_entry_addr = P4_ALGO_ENTRY_ADDR; - break; - case MSP432E401Y: - case MSP432E411Y: - case MSP432E4X_GUESS: - loader_code = msp432e4x_algo; - loader_size = sizeof(msp432e4x_algo); - algo_entry_addr = E4_ALGO_ENTRY_ADDR; - break; + case MSP432P401X: + case MSP432P401X_DEPR: + case MSP432P401X_GUESS: + default: + loader_code = msp432p401x_algo; + loader_size = sizeof(msp432p401x_algo); + algo_entry_addr = P4_ALGO_ENTRY_ADDR; + break; + case MSP432P411X: + case MSP432P411X_GUESS: + loader_code = msp432p411x_algo; + loader_size = sizeof(msp432p411x_algo); + algo_entry_addr = P4_ALGO_ENTRY_ADDR; + break; + case MSP432E401Y: + case MSP432E411Y: + case MSP432E4X_GUESS: + loader_code = msp432e4x_algo; + loader_size = sizeof(msp432e4x_algo); + algo_entry_addr = E4_ALGO_ENTRY_ADDR; + break; } /* Issue warnings if this is a device we may not be able to flash */ @@ -980,43 +980,43 @@ static int msp432_info(struct flash_bank *bank, struct command_invocation *cmd) struct msp432_bank *msp432_bank = bank->driver_priv; switch (msp432_bank->device_type) { - case MSP432P401X_DEPR: - if (msp432_bank->device_id == 0xFFFF) { - /* Very early pre-production silicon currently deprecated */ - command_print_sameline(cmd, "MSP432P401x pre-production device (deprecated silicon)\n" - SUPPORT_MESSAGE); - } else { - /* Revision A or B silicon, also deprecated */ - command_print_sameline(cmd, "MSP432P401x Device Rev %c (deprecated silicon)\n" - SUPPORT_MESSAGE, (char)msp432_bank->hardware_rev); - } - break; - case MSP432P401X: - command_print_sameline(cmd, "MSP432P401x Device Rev %c\n", - (char)msp432_bank->hardware_rev); - break; - case MSP432P411X: - command_print_sameline(cmd, "MSP432P411x Device Rev %c\n", - (char)msp432_bank->hardware_rev); - break; - case MSP432E401Y: - command_print_sameline(cmd, "MSP432E401Y Device\n"); - break; - case MSP432E411Y: - command_print_sameline(cmd, "MSP432E411Y Device\n"); - break; - case MSP432E4X_GUESS: - command_print_sameline(cmd, - "Unrecognized MSP432E4 DID0 and DID1 IDs (%08" PRIX32 ", %08" PRIX32 ")", - msp432_bank->device_id, msp432_bank->hardware_rev); - break; - case MSP432P401X_GUESS: - case MSP432P411X_GUESS: - default: - command_print_sameline(cmd, - "Unrecognized MSP432P4 Device ID and Hardware Rev (%04" PRIX32 ", %02" PRIX32 ")", - msp432_bank->device_id, msp432_bank->hardware_rev); - break; + case MSP432P401X_DEPR: + if (msp432_bank->device_id == 0xFFFF) { + /* Very early pre-production silicon currently deprecated */ + command_print_sameline(cmd, "MSP432P401x pre-production device (deprecated silicon)\n" + SUPPORT_MESSAGE); + } else { + /* Revision A or B silicon, also deprecated */ + command_print_sameline(cmd, "MSP432P401x Device Rev %c (deprecated silicon)\n" + SUPPORT_MESSAGE, (char)msp432_bank->hardware_rev); + } + break; + case MSP432P401X: + command_print_sameline(cmd, "MSP432P401x Device Rev %c\n", + (char)msp432_bank->hardware_rev); + break; + case MSP432P411X: + command_print_sameline(cmd, "MSP432P411x Device Rev %c\n", + (char)msp432_bank->hardware_rev); + break; + case MSP432E401Y: + command_print_sameline(cmd, "MSP432E401Y Device\n"); + break; + case MSP432E411Y: + command_print_sameline(cmd, "MSP432E411Y Device\n"); + break; + case MSP432E4X_GUESS: + command_print_sameline(cmd, + "Unrecognized MSP432E4 DID0 and DID1 IDs (%08" PRIX32 ", %08" PRIX32 ")", + msp432_bank->device_id, msp432_bank->hardware_rev); + break; + case MSP432P401X_GUESS: + case MSP432P411X_GUESS: + default: + command_print_sameline(cmd, + "Unrecognized MSP432P4 Device ID and Hardware Rev (%04" PRIX32 ", %02" PRIX32 ")", + msp432_bank->device_id, msp432_bank->hardware_rev); + break; } return ERROR_OK; diff --git a/src/flash/nor/ocl.c b/src/flash/nor/ocl.c index f9d981ef9..6db7368f9 100644 --- a/src/flash/nor/ocl.c +++ b/src/flash/nor/ocl.c @@ -132,21 +132,21 @@ static int ocl_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t of /* copy data to DCC buffer in proper byte order and properly aligned */ for (i = 0; i < runlen; i++) { switch (byteofs++) { - case 0: - *dcc_bufptr &= *(buffer++) | 0xffffff00; - break; - case 1: - *dcc_bufptr &= ((*(buffer++)) << 8) | 0xffff00ff; - break; - case 2: - *dcc_bufptr &= ((*(buffer++)) << 16) | 0xff00ffff; - break; - case 3: - *dcc_bufptr &= ((*(buffer++)) << 24) | 0x00ffffff; - chksum ^= *(dcc_bufptr++); - *dcc_bufptr = 0xffffffff; - byteofs = 0; - break; + case 0: + *dcc_bufptr &= *(buffer++) | 0xffffff00; + break; + case 1: + *dcc_bufptr &= ((*(buffer++)) << 8) | 0xffff00ff; + break; + case 2: + *dcc_bufptr &= ((*(buffer++)) << 16) | 0xff00ffff; + break; + case 3: + *dcc_bufptr &= ((*(buffer++)) << 24) | 0x00ffffff; + chksum ^= *(dcc_bufptr++); + *dcc_bufptr = 0xffffffff; + byteofs = 0; + break; } } diff --git a/src/flash/nor/psoc6.c b/src/flash/nor/psoc6.c index 662910aa0..3c7b06666 100644 --- a/src/flash/nor/psoc6.c +++ b/src/flash/nor/psoc6.c @@ -420,17 +420,17 @@ static int psoc6_protect_check(struct flash_bank *bank) return hr; switch (psoc6_info->protection) { - case PROTECTION_VIRGIN: - case PROTECTION_NORMAL: - is_protected = 0; - break; + case PROTECTION_VIRGIN: + case PROTECTION_NORMAL: + is_protected = 0; + break; - case PROTECTION_UNKNOWN: - case PROTECTION_SECURE: - case PROTECTION_DEAD: - default: - is_protected = 1; - break; + case PROTECTION_UNKNOWN: + case PROTECTION_SECURE: + case PROTECTION_DEAD: + default: + is_protected = 1; + break; } for (unsigned int i = 0; i < bank->num_sectors; i++) @@ -463,17 +463,17 @@ static int psoc6_protect(struct flash_bank *bank, int set, unsigned int first, static const char *protection_to_str(uint8_t protection) { switch (protection) { - case PROTECTION_VIRGIN: - return "VIRGIN"; - case PROTECTION_NORMAL: - return "NORMAL"; - case PROTECTION_SECURE: - return "SECURE"; - case PROTECTION_DEAD: - return "DEAD"; - case PROTECTION_UNKNOWN: - default: - return "UNKNOWN"; + case PROTECTION_VIRGIN: + return "VIRGIN"; + case PROTECTION_NORMAL: + return "NORMAL"; + case PROTECTION_SECURE: + return "SECURE"; + case PROTECTION_DEAD: + return "DEAD"; + case PROTECTION_UNKNOWN: + default: + return "UNKNOWN"; } } diff --git a/src/flash/nor/stellaris.c b/src/flash/nor/stellaris.c index d0a32f970..bf598b117 100644 --- a/src/flash/nor/stellaris.c +++ b/src/flash/nor/stellaris.c @@ -608,30 +608,30 @@ static void stellaris_read_clock_info(struct flash_bank *bank) stellaris_info->mck_desc = ""; switch (oscsrc) { - case 0: /* MOSC */ - mainfreq = rcc_xtal[xtal]; - break; - case 1: /* IOSC */ - mainfreq = stellaris_info->iosc_freq; - stellaris_info->mck_desc = stellaris_info->iosc_desc; - break; - case 2: /* IOSC/4 */ - mainfreq = stellaris_info->iosc_freq / 4; - stellaris_info->mck_desc = stellaris_info->iosc_desc; - break; - case 3: /* lowspeed */ - /* Sandstorm doesn't have this 30K +/- 30% osc */ - mainfreq = 30000; - stellaris_info->mck_desc = " (±30%)"; - break; - case 8: /* hibernation osc */ - /* not all parts support hibernation */ - mainfreq = 32768; - break; + case 0: /* MOSC */ + mainfreq = rcc_xtal[xtal]; + break; + case 1: /* IOSC */ + mainfreq = stellaris_info->iosc_freq; + stellaris_info->mck_desc = stellaris_info->iosc_desc; + break; + case 2: /* IOSC/4 */ + mainfreq = stellaris_info->iosc_freq / 4; + stellaris_info->mck_desc = stellaris_info->iosc_desc; + break; + case 3: /* lowspeed */ + /* Sandstorm doesn't have this 30K +/- 30% osc */ + mainfreq = 30000; + stellaris_info->mck_desc = " (±30%)"; + break; + case 8: /* hibernation osc */ + /* not all parts support hibernation */ + mainfreq = 32768; + break; - default: /* NOTREACHED */ - mainfreq = 0; - break; + default: /* NOTREACHED */ + mainfreq = 0; + break; } /* PLL is used if it's not bypassed; its output is 200 MHz @@ -702,35 +702,35 @@ static int stellaris_read_part_info(struct flash_bank *bank) } switch (stellaris_info->target_class) { - case 0: /* Sandstorm */ - /* - * Current (2009-August) parts seem to be rev C2 and use 12 MHz. - * Parts before rev C0 used 15 MHz; some C0 parts use 15 MHz - * (LM3S618), but some other C0 parts are 12 MHz (LM3S811). - */ - if (((did0 >> 8) & 0xff) < 2) { - stellaris_info->iosc_freq = 15000000; - stellaris_info->iosc_desc = " (±50%)"; - } - break; + case 0: /* Sandstorm */ + /* + * Current (2009-August) parts seem to be rev C2 and use 12 MHz. + * Parts before rev C0 used 15 MHz; some C0 parts use 15 MHz + * (LM3S618), but some other C0 parts are 12 MHz (LM3S811). + */ + if (((did0 >> 8) & 0xff) < 2) { + stellaris_info->iosc_freq = 15000000; + stellaris_info->iosc_desc = " (±50%)"; + } + break; - case 1: /* Fury */ - break; + case 1: /* Fury */ + break; - case 4: /* Tempest */ - case 5: /* Blizzard */ - case 6: /* Firestorm */ - case 0xa: /* Snowflake */ - stellaris_info->iosc_freq = 16000000; /* +/- 1% */ - stellaris_info->iosc_desc = " (±1%)"; - /* FALL THROUGH */ + case 4: /* Tempest */ + case 5: /* Blizzard */ + case 6: /* Firestorm */ + case 0xa: /* Snowflake */ + stellaris_info->iosc_freq = 16000000; /* +/- 1% */ + stellaris_info->iosc_desc = " (±1%)"; + /* FALL THROUGH */ - case 3: /* DustDevil */ - stellaris_info->xtal_mask = 0x1f; - break; + case 3: /* DustDevil */ + stellaris_info->xtal_mask = 0x1f; + break; - default: - LOG_WARNING("Unknown did0 class"); + default: + LOG_WARNING("Unknown did0 class"); } for (i = 0; stellaris_parts[i].partno; i++) { diff --git a/src/flash/nor/stmqspi.c b/src/flash/nor/stmqspi.c index df58f6c55..bd72fe050 100644 --- a/src/flash/nor/stmqspi.c +++ b/src/flash/nor/stmqspi.c @@ -1978,24 +1978,24 @@ static int read_flash_id(struct flash_bank *bank, uint32_t *id1, uint32_t *id2) /* Read id: one particular flash chip (N25Q128) switches back to SPI mode when receiving * SPI_FLASH_READ_ID in QPI mode, hence try SPIFLASH_READ_MID first */ switch (type) { - case 0: - if (IS_OCTOSPI) - retval = octospi_cmd(bank, OCTOSPI_READ_MODE, - OCTOSPI_CCR_READ_MID, SPIFLASH_READ_MID); - else - retval = target_write_u32(target, io_base + QSPI_CCR, QSPI_CCR_READ_MID); - break; + case 0: + if (IS_OCTOSPI) + retval = octospi_cmd(bank, OCTOSPI_READ_MODE, + OCTOSPI_CCR_READ_MID, SPIFLASH_READ_MID); + else + retval = target_write_u32(target, io_base + QSPI_CCR, QSPI_CCR_READ_MID); + break; - case 1: - if (IS_OCTOSPI) - retval = octospi_cmd(bank, OCTOSPI_READ_MODE, - OCTOSPI_CCR_READ_ID, SPIFLASH_READ_ID); - else - retval = target_write_u32(target, io_base + QSPI_CCR, QSPI_CCR_READ_ID); - break; + case 1: + if (IS_OCTOSPI) + retval = octospi_cmd(bank, OCTOSPI_READ_MODE, + OCTOSPI_CCR_READ_ID, SPIFLASH_READ_ID); + else + retval = target_write_u32(target, io_base + QSPI_CCR, QSPI_CCR_READ_ID); + break; - default: - return ERROR_FAIL; + default: + return ERROR_FAIL; } if (retval != ERROR_OK) diff --git a/src/flash/nor/stmsmi.c b/src/flash/nor/stmsmi.c index 1aa244728..85f358078 100644 --- a/src/flash/nor/stmsmi.c +++ b/src/flash/nor/stmsmi.c @@ -531,21 +531,21 @@ static int stmsmi_probe(struct flash_bank *bank) } switch (bank->base - target_device->smi_base) { - case 0: - stmsmi_info->bank_num = SMI_SEL_BANK0; - break; - case SMI_BANK_SIZE: - stmsmi_info->bank_num = SMI_SEL_BANK1; - break; - case 2*SMI_BANK_SIZE: - stmsmi_info->bank_num = SMI_SEL_BANK2; - break; - case 3*SMI_BANK_SIZE: - stmsmi_info->bank_num = SMI_SEL_BANK3; - break; - default: - LOG_ERROR("Invalid SMI base address " TARGET_ADDR_FMT, bank->base); - return ERROR_FAIL; + case 0: + stmsmi_info->bank_num = SMI_SEL_BANK0; + break; + case SMI_BANK_SIZE: + stmsmi_info->bank_num = SMI_SEL_BANK1; + break; + case 2 * SMI_BANK_SIZE: + stmsmi_info->bank_num = SMI_SEL_BANK2; + break; + case 3 * SMI_BANK_SIZE: + stmsmi_info->bank_num = SMI_SEL_BANK3; + break; + default: + LOG_ERROR("Invalid SMI base address " TARGET_ADDR_FMT, bank->base); + return ERROR_FAIL; } io_base = target_device->io_base; stmsmi_info->io_base = io_base; diff --git a/src/flash/nor/str7x.c b/src/flash/nor/str7x.c index 5ba5bfa6d..0177095cb 100644 --- a/src/flash/nor/str7x.c +++ b/src/flash/nor/str7x.c @@ -131,21 +131,21 @@ static int str7x_build_block_list(struct flash_bank *bank) int b0_sectors = 0, b1_sectors = 0; switch (bank->size) { - case 16 * 1024: - b1_sectors = 2; - break; - case 64 * 1024: - b0_sectors = 5; - break; - case 128 * 1024: - b0_sectors = 6; - break; - case 256 * 1024: - b0_sectors = 8; - break; - default: - LOG_ERROR("BUG: unknown bank->size encountered"); - exit(-1); + case 16 * 1024: + b1_sectors = 2; + break; + case 64 * 1024: + b0_sectors = 5; + break; + case 128 * 1024: + b0_sectors = 6; + break; + case 256 * 1024: + b0_sectors = 8; + break; + default: + LOG_ERROR("BUG: unknown bank->size encountered"); + exit(-1); } num_sectors = b0_sectors + b1_sectors; diff --git a/src/flash/nor/str9x.c b/src/flash/nor/str9x.c index 1a26b839e..9efac241a 100644 --- a/src/flash/nor/str9x.c +++ b/src/flash/nor/str9x.c @@ -66,36 +66,36 @@ static int str9x_build_block_list(struct flash_bank *bank) str9x_info->bank1 = 0; switch (bank->size) { - case (256 * 1024): - b0_sectors = 4; - break; - case (512 * 1024): - b0_sectors = 8; - break; - case (1024 * 1024): - bank1start = 0x00100000; - str9x_info->variant = 1; - b0_sectors = 16; - break; - case (2048 * 1024): - bank1start = 0x00200000; - str9x_info->variant = 1; - b0_sectors = 32; - break; - case (128 * 1024): - str9x_info->variant = 1; - str9x_info->bank1 = 1; - b1_sectors = 8; - bank1start = bank->base; - break; - case (32 * 1024): - str9x_info->bank1 = 1; - b1_sectors = 4; - bank1start = bank->base; - break; - default: - LOG_ERROR("BUG: unknown bank->size encountered"); - exit(-1); + case (256 * 1024): + b0_sectors = 4; + break; + case (512 * 1024): + b0_sectors = 8; + break; + case (1024 * 1024): + bank1start = 0x00100000; + str9x_info->variant = 1; + b0_sectors = 16; + break; + case (2048 * 1024): + bank1start = 0x00200000; + str9x_info->variant = 1; + b0_sectors = 32; + break; + case (128 * 1024): + str9x_info->variant = 1; + str9x_info->bank1 = 1; + b1_sectors = 8; + bank1start = bank->base; + break; + case (32 * 1024): + str9x_info->bank1 = 1; + b1_sectors = 4; + bank1start = bank->base; + break; + default: + LOG_ERROR("BUG: unknown bank->size encountered"); + exit(-1); } num_sectors = b0_sectors + b1_sectors; diff --git a/src/flash/nor/str9xpec.c b/src/flash/nor/str9xpec.c index a5058b405..be0089879 100644 --- a/src/flash/nor/str9xpec.c +++ b/src/flash/nor/str9xpec.c @@ -206,28 +206,28 @@ static int str9xpec_build_block_list(struct flash_bank *bank) int b1_size = 0x2000; switch (bank->size) { - case (256 * 1024): - b0_sectors = 4; - break; - case (512 * 1024): - b0_sectors = 8; - break; - case (1024 * 1024): - b0_sectors = 16; - break; - case (2048 * 1024): - b0_sectors = 32; - break; - case (128 * 1024): - b1_size = 0x4000; - b1_sectors = 8; - break; - case (32 * 1024): - b1_sectors = 4; - break; - default: - LOG_ERROR("BUG: unknown bank->size encountered"); - exit(-1); + case (256 * 1024): + b0_sectors = 4; + break; + case (512 * 1024): + b0_sectors = 8; + break; + case (1024 * 1024): + b0_sectors = 16; + break; + case (2048 * 1024): + b0_sectors = 32; + break; + case (128 * 1024): + b1_size = 0x4000; + b1_sectors = 8; + break; + case (32 * 1024): + b1_sectors = 4; + break; + default: + LOG_ERROR("BUG: unknown bank->size encountered"); + exit(-1); } num_sectors = b0_sectors + b1_sectors; diff --git a/src/flash/nor/tcl.c b/src/flash/nor/tcl.c index 0d41e49c8..6161f5d26 100644 --- a/src/flash/nor/tcl.c +++ b/src/flash/nor/tcl.c @@ -535,20 +535,20 @@ COMMAND_HANDLER(handle_flash_fill_command) return retval; switch (CMD_NAME[4]) { - case 'd': - wordsize = 8; - break; - case 'w': - wordsize = 4; - break; - case 'h': - wordsize = 2; - break; - case 'b': - wordsize = 1; - break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; + case 'd': + wordsize = 8; + break; + case 'w': + wordsize = 4; + break; + case 'h': + wordsize = 2; + break; + case 'b': + wordsize = 1; + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } if ((wordsize < sizeof(pattern)) && (pattern >> (8 * wordsize) != 0)) { @@ -588,25 +588,25 @@ COMMAND_HANDLER(handle_flash_fill_command) uint8_t *ptr = buffer + padding_at_start; switch (wordsize) { - case 8: - for (i = 0; i < count; i++, ptr += wordsize) - target_buffer_set_u64(target, ptr, pattern); - break; - case 4: - for (i = 0; i < count; i++, ptr += wordsize) - target_buffer_set_u32(target, ptr, pattern); - break; - case 2: - for (i = 0; i < count; i++, ptr += wordsize) - target_buffer_set_u16(target, ptr, pattern); - break; - case 1: - memset(ptr, pattern, count); - ptr += count; - break; - default: - LOG_ERROR("BUG: can't happen"); - exit(-1); + case 8: + for (i = 0; i < count; i++, ptr += wordsize) + target_buffer_set_u64(target, ptr, pattern); + break; + case 4: + for (i = 0; i < count; i++, ptr += wordsize) + target_buffer_set_u32(target, ptr, pattern); + break; + case 2: + for (i = 0; i < count; i++, ptr += wordsize) + target_buffer_set_u16(target, ptr, pattern); + break; + case 1: + memset(ptr, pattern, count); + ptr += count; + break; + default: + LOG_ERROR("BUG: can't happen"); + exit(-1); } if (padding_at_end) { @@ -631,18 +631,18 @@ COMMAND_HANDLER(handle_flash_fill_command) uint64_t readback = 0; switch (wordsize) { - case 8: - readback = target_buffer_get_u64(target, ptr); - break; - case 4: - readback = target_buffer_get_u32(target, ptr); - break; - case 2: - readback = target_buffer_get_u16(target, ptr); - break; - case 1: - readback = *ptr; - break; + case 8: + readback = target_buffer_get_u64(target, ptr); + break; + case 4: + readback = target_buffer_get_u32(target, ptr); + break; + case 2: + readback = target_buffer_get_u16(target, ptr); + break; + case 1: + readback = *ptr; + break; } if (readback != pattern) { LOG_ERROR( @@ -683,17 +683,17 @@ COMMAND_HANDLER(handle_flash_md_command) unsigned int wordsize; switch (CMD_NAME[2]) { - case 'w': - wordsize = 4; - break; - case 'h': - wordsize = 2; - break; - case 'b': - wordsize = 1; - break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; + case 'w': + wordsize = 4; + break; + case 'h': + wordsize = 2; + break; + case 'b': + wordsize = 1; + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } if (count == 0) diff --git a/src/flash/nor/tms470.c b/src/flash/nor/tms470.c index ba730daaf..fa0b5b68e 100644 --- a/src/flash/nor/tms470.c +++ b/src/flash/nor/tms470.c @@ -148,100 +148,100 @@ static int tms470_read_part_info(struct flash_bank *bank) * bank structure. */ switch (part_number) { - case 0x0a: - part_name = "TMS470R1A256"; + case 0x0a: + part_name = "TMS470R1A256"; - if (bank->base >= 0x00040000) { - LOG_ERROR("No %s flash bank contains base address " - TARGET_ADDR_FMT ".", - part_name, - bank->base); - return ERROR_FLASH_OPERATION_FAILED; - } + if (bank->base >= 0x00040000) { + LOG_ERROR("No %s flash bank contains base address " + TARGET_ADDR_FMT ".", + part_name, + bank->base); + return ERROR_FLASH_OPERATION_FAILED; + } + tms470_info->ordinal = 0; + bank->base = 0x00000000; + bank->size = 256 * 1024; + bank->num_sectors = TMS470R1A256_NUM_SECTORS; + bank->sectors = malloc(sizeof(tms470r1a256_sectors)); + if (!bank->sectors) + return ERROR_FLASH_OPERATION_FAILED; + (void)memcpy(bank->sectors, tms470r1a256_sectors, sizeof(tms470r1a256_sectors)); + break; + + case 0x2b: + part_name = "TMS470R1A288"; + + if (bank->base < 0x00008000) { tms470_info->ordinal = 0; bank->base = 0x00000000; - bank->size = 256 * 1024; - bank->num_sectors = TMS470R1A256_NUM_SECTORS; - bank->sectors = malloc(sizeof(tms470r1a256_sectors)); + bank->size = 32 * 1024; + bank->num_sectors = TMS470R1A288_BANK0_NUM_SECTORS; + bank->sectors = malloc(sizeof(tms470r1a288_bank0_sectors)); if (!bank->sectors) return ERROR_FLASH_OPERATION_FAILED; - (void)memcpy(bank->sectors, tms470r1a256_sectors, sizeof(tms470r1a256_sectors)); - break; - - case 0x2b: - part_name = "TMS470R1A288"; - - if (bank->base < 0x00008000) { - tms470_info->ordinal = 0; - bank->base = 0x00000000; - bank->size = 32 * 1024; - bank->num_sectors = TMS470R1A288_BANK0_NUM_SECTORS; - bank->sectors = malloc(sizeof(tms470r1a288_bank0_sectors)); - if (!bank->sectors) - return ERROR_FLASH_OPERATION_FAILED; - (void)memcpy(bank->sectors, tms470r1a288_bank0_sectors, - sizeof(tms470r1a288_bank0_sectors)); - } else if ((bank->base >= 0x00040000) && (bank->base < 0x00080000)) { - tms470_info->ordinal = 1; - bank->base = 0x00040000; - bank->size = 256 * 1024; - bank->num_sectors = TMS470R1A288_BANK1_NUM_SECTORS; - bank->sectors = malloc(sizeof(tms470r1a288_bank1_sectors)); - if (!bank->sectors) - return ERROR_FLASH_OPERATION_FAILED; - (void)memcpy(bank->sectors, tms470r1a288_bank1_sectors, - sizeof(tms470r1a288_bank1_sectors)); - } else { - LOG_ERROR("No %s flash bank contains base address " TARGET_ADDR_FMT ".", - part_name, bank->base); + (void)memcpy(bank->sectors, tms470r1a288_bank0_sectors, + sizeof(tms470r1a288_bank0_sectors)); + } else if ((bank->base >= 0x00040000) && (bank->base < 0x00080000)) { + tms470_info->ordinal = 1; + bank->base = 0x00040000; + bank->size = 256 * 1024; + bank->num_sectors = TMS470R1A288_BANK1_NUM_SECTORS; + bank->sectors = malloc(sizeof(tms470r1a288_bank1_sectors)); + if (!bank->sectors) return ERROR_FLASH_OPERATION_FAILED; - } - break; - - case 0x2d: - part_name = "TMS470R1A384"; - - if (bank->base < 0x00020000) { - tms470_info->ordinal = 0; - bank->base = 0x00000000; - bank->size = 128 * 1024; - bank->num_sectors = TMS470R1A384_BANK0_NUM_SECTORS; - bank->sectors = malloc(sizeof(tms470r1a384_bank0_sectors)); - if (!bank->sectors) - return ERROR_FLASH_OPERATION_FAILED; - (void)memcpy(bank->sectors, tms470r1a384_bank0_sectors, - sizeof(tms470r1a384_bank0_sectors)); - } else if ((bank->base >= 0x00020000) && (bank->base < 0x00040000)) { - tms470_info->ordinal = 1; - bank->base = 0x00020000; - bank->size = 128 * 1024; - bank->num_sectors = TMS470R1A384_BANK1_NUM_SECTORS; - bank->sectors = malloc(sizeof(tms470r1a384_bank1_sectors)); - if (!bank->sectors) - return ERROR_FLASH_OPERATION_FAILED; - (void)memcpy(bank->sectors, tms470r1a384_bank1_sectors, - sizeof(tms470r1a384_bank1_sectors)); - } else if ((bank->base >= 0x00040000) && (bank->base < 0x00060000)) { - tms470_info->ordinal = 2; - bank->base = 0x00040000; - bank->size = 128 * 1024; - bank->num_sectors = TMS470R1A384_BANK2_NUM_SECTORS; - bank->sectors = malloc(sizeof(tms470r1a384_bank2_sectors)); - if (!bank->sectors) - return ERROR_FLASH_OPERATION_FAILED; - (void)memcpy(bank->sectors, tms470r1a384_bank2_sectors, - sizeof(tms470r1a384_bank2_sectors)); - } else { - LOG_ERROR("No %s flash bank contains base address " TARGET_ADDR_FMT ".", - part_name, bank->base); - return ERROR_FLASH_OPERATION_FAILED; - } - break; - - default: - LOG_WARNING("Could not identify part 0x%02" PRIx32 " as a member of the TMS470 family.", - part_number); + (void)memcpy(bank->sectors, tms470r1a288_bank1_sectors, + sizeof(tms470r1a288_bank1_sectors)); + } else { + LOG_ERROR("No %s flash bank contains base address " TARGET_ADDR_FMT ".", + part_name, bank->base); return ERROR_FLASH_OPERATION_FAILED; + } + break; + + case 0x2d: + part_name = "TMS470R1A384"; + + if (bank->base < 0x00020000) { + tms470_info->ordinal = 0; + bank->base = 0x00000000; + bank->size = 128 * 1024; + bank->num_sectors = TMS470R1A384_BANK0_NUM_SECTORS; + bank->sectors = malloc(sizeof(tms470r1a384_bank0_sectors)); + if (!bank->sectors) + return ERROR_FLASH_OPERATION_FAILED; + (void)memcpy(bank->sectors, tms470r1a384_bank0_sectors, + sizeof(tms470r1a384_bank0_sectors)); + } else if ((bank->base >= 0x00020000) && (bank->base < 0x00040000)) { + tms470_info->ordinal = 1; + bank->base = 0x00020000; + bank->size = 128 * 1024; + bank->num_sectors = TMS470R1A384_BANK1_NUM_SECTORS; + bank->sectors = malloc(sizeof(tms470r1a384_bank1_sectors)); + if (!bank->sectors) + return ERROR_FLASH_OPERATION_FAILED; + (void)memcpy(bank->sectors, tms470r1a384_bank1_sectors, + sizeof(tms470r1a384_bank1_sectors)); + } else if ((bank->base >= 0x00040000) && (bank->base < 0x00060000)) { + tms470_info->ordinal = 2; + bank->base = 0x00040000; + bank->size = 128 * 1024; + bank->num_sectors = TMS470R1A384_BANK2_NUM_SECTORS; + bank->sectors = malloc(sizeof(tms470r1a384_bank2_sectors)); + if (!bank->sectors) + return ERROR_FLASH_OPERATION_FAILED; + (void)memcpy(bank->sectors, tms470r1a384_bank2_sectors, + sizeof(tms470r1a384_bank2_sectors)); + } else { + LOG_ERROR("No %s flash bank contains base address " TARGET_ADDR_FMT ".", + part_name, bank->base); + return ERROR_FLASH_OPERATION_FAILED; + } + break; + + default: + LOG_WARNING("Could not identify part 0x%02" PRIx32 " as a member of the TMS470 family.", + part_number); + return ERROR_FLASH_OPERATION_FAILED; } /* turn off memory selects */ diff --git a/src/flash/nor/xcf.c b/src/flash/nor/xcf.c index 4011fa42b..04ee0d34a 100644 --- a/src/flash/nor/xcf.c +++ b/src/flash/nor/xcf.c @@ -87,14 +87,14 @@ static const char *product_name(const struct flash_bank *bank) { switch (bank->target->tap->idcode & ID_MEANINGFUL_MASK) { - case ID_XCF08P: - return xcf_name_list[0]; - case ID_XCF16P: - return xcf_name_list[1]; - case ID_XCF32P: - return xcf_name_list[2]; - default: - return xcf_name_list[3]; + case ID_XCF08P: + return xcf_name_list[0]; + case ID_XCF16P: + return xcf_name_list[1]; + case ID_XCF32P: + return xcf_name_list[2]; + default: + return xcf_name_list[3]; } } @@ -601,18 +601,18 @@ static int xcf_probe(struct flash_bank *bank) /* guess number of blocks using chip ID */ id = bank->target->tap->idcode; switch (id & ID_MEANINGFUL_MASK) { - case ID_XCF08P: - bank->num_sectors = 1; - break; - case ID_XCF16P: - bank->num_sectors = 2; - break; - case ID_XCF32P: - bank->num_sectors = 4; - break; - default: - LOG_ERROR("Unknown flash device ID 0x%" PRIX32, id); - return ERROR_FAIL; + case ID_XCF08P: + bank->num_sectors = 1; + break; + case ID_XCF16P: + bank->num_sectors = 2; + break; + case ID_XCF32P: + bank->num_sectors = 4; + break; + default: + LOG_ERROR("Unknown flash device ID 0x%" PRIX32, id); + return ERROR_FAIL; } bank->sectors = malloc(bank->num_sectors * sizeof(struct flash_sector));