forked from auracaster/openocd
flash/nor: add support for Nuvoton NPCX series flash
Added NPCX flash driver to support the Nuvoton NPCX series microcontrollers. Add config file for NPCX series. Change-Id: Ia10b019a3521f59ad1e10ccdc56827ba30c3eac8 Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com> Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://review.openocd.org/c/openocd/+/5950 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
This commit is contained in:
Wealian Liao
committed by
Oleksij Rempel
Oleksij Rempel
parent
a098816a65
commit
385eedfc6f
@@ -0,0 +1,65 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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BIN2C = ../../../../src/helper/bin2char.sh
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# Toolchain used in makefile
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CROSS_COMPILE ?= arm-none-eabi-
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CC = $(CROSS_COMPILE)gcc
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CPLUS = $(CROSS_COMPILE)g++
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CPP = $(CROSS_COMPILE)cpp
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LD = $(CROSS_COMPILE)gcc
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AS = $(CROSS_COMPILE)as
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OBJCOPY = $(CROSS_COMPILE)objcopy
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OBJDUMP = $(CROSS_COMPILE)objdump
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OBJSIZE = $(CROSS_COMPILE)size
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TARGET = npcx_algo
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OBJS := npcx_flash.o
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FLAGS = -mthumb -Os -ffunction-sections -fdata-sections -g -gdwarf-3 --specs=nano.specs
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FLAGS += -gstrict-dwarf -Wall -fno-strict-aliasing --asm
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CFLAGS = -c -I. -mcpu=cortex-m4 -fpack-struct
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PRE_LD_FILE = npcx_flash.lds
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LD_FILE = npcx_flash_generated.lds
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LDFLAGS = -Wl,-Map,lfw.map -Wl,-T$(LD_FILE) -nostartfiles
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all: $(TARGET).inc
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# Implicit rules
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%.o: %.c
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-@ echo CC $@ from $<
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@$(CC) $< $(FLAGS) $(CFLAGS) -o $@
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$(LD_FILE): $(PRE_LD_FILE)
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-@ echo Generate $@ from $<
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-@$(CPP) $(PRE_LD_FILE) | grep -v '^#' >>$(LD_FILE)
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$(TARGET).elf: $(OBJS) $(LD_FILE)
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-@ echo LD $@ from $<
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@$(LD) -o $@ $< $(FLAGS) $(LDFLAGS)
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%.bin: %.elf
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-@ echo OBJCOPY $@ from $<
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-@ $(OBJCOPY) $< -O binary $@
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-@ $(OBJSIZE) $< --format=berkeley
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%.inc: %.bin
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@echo 'Building target: $@'
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@echo 'Invoking Bin2Char Script'
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$(BIN2C) < $< > $@
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rm $< $*.elf
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@echo 'Finished building target: $@'
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@echo ' '
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clean:
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@echo 'Cleaning Targets and Build Artifacts'
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rm -rf *.inc *.bin *.elf *.map
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rm -rf *.o *.d
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rm -rf $(LD_FILE)
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@echo 'Finished clean'
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@echo ' '
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.PRECIOUS: %.bin
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.PHONY: all clean
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@@ -0,0 +1,60 @@
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/* Autogenerated with ../../../../src/helper/bin2char.sh */
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||||
@@ -0,0 +1,342 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2020 by Nuvoton Technology Corporation
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* Mulin Chao <mlchao@nuvoton.com>
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* Wealian Liao <WHLIAO@nuvoton.com>
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*/
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#include <stdint.h>
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#include <string.h>
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#include "npcx_flash.h"
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/*----------------------------------------------------------------------------
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* NPCX flash driver
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*----------------------------------------------------------------------------*/
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static void flash_execute_cmd(uint8_t code, uint8_t cts)
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{
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/* Set UMA code */
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NPCX_UMA_CODE = code;
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/* Execute UMA flash transaction by CTS setting */
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NPCX_UMA_CTS = cts;
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/* Wait for transaction completed */
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while (NPCX_IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE))
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;
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}
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static void flash_cs_level(uint8_t level)
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{
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/* Program chip select pin to high/low level */
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if (level)
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NPCX_SET_BIT(NPCX_UMA_ECTS, NPCX_UMA_ECTS_SW_CS1);
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else
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NPCX_CLEAR_BIT(NPCX_UMA_ECTS, NPCX_UMA_ECTS_SW_CS1);
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}
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static void flash_set_address(uint32_t dest_addr)
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{
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uint8_t *addr = (uint8_t *)&dest_addr;
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/* Set target flash address */
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NPCX_UMA_AB2 = addr[2];
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NPCX_UMA_AB1 = addr[1];
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NPCX_UMA_AB0 = addr[0];
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}
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void delay(uint32_t i)
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{
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while (i--)
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;
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}
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static int flash_wait_ready(uint32_t timeout)
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{
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/* Chip Select down. -- Burst mode */
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flash_cs_level(0);
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/* Command for Read status register */
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flash_execute_cmd(NPCX_CMD_READ_STATUS_REG, NPCX_MASK_CMD_ONLY);
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while (timeout > 0) {
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/* Read status register */
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NPCX_UMA_CTS = NPCX_MASK_RD_1BYTE;
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while (NPCX_IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE))
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;
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if (!(NPCX_UMA_DB0 & NPCX_SPI_FLASH_SR1_BUSY))
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break;
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if (--timeout > 0)
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delay(100);
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}; /* Wait for Busy clear */
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/* Chip Select high. */
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flash_cs_level(1);
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if (timeout == 0)
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return NPCX_FLASH_STATUS_FAILED_TIMEOUT;
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return NPCX_FLASH_STATUS_OK;
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}
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static int flash_write_enable(void)
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{
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/* Write enable command */
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flash_execute_cmd(NPCX_CMD_WRITE_EN, NPCX_MASK_CMD_ONLY);
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/* Wait for flash is not busy */
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int status = flash_wait_ready(NPCX_FLASH_ABORT_TIMEOUT);
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if (status != NPCX_FLASH_STATUS_OK)
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return status;
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if (NPCX_UMA_DB0 & NPCX_SPI_FLASH_SR1_WEL)
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return NPCX_FLASH_STATUS_OK;
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else
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return NPCX_FLASH_STATUS_FAILED;
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}
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static void flash_burst_write(uint32_t dest_addr, uint16_t bytes,
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const uint8_t *data)
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{
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/* Chip Select down -- Burst mode */
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flash_cs_level(0);
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/* Set write address */
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flash_set_address(dest_addr);
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/* Start programming */
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flash_execute_cmd(NPCX_CMD_FLASH_PROGRAM, NPCX_MASK_CMD_WR_ADR);
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for (uint32_t i = 0; i < bytes; i++) {
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flash_execute_cmd(*data, NPCX_MASK_CMD_WR_ONLY);
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data++;
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}
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/* Chip Select up */
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flash_cs_level(1);
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}
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/* The data to write cannot cross 256 Bytes boundary */
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static int flash_program_write(uint32_t addr, uint32_t size,
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const uint8_t *data)
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{
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int status = flash_write_enable();
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if (status != NPCX_FLASH_STATUS_OK)
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return status;
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flash_burst_write(addr, size, data);
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return flash_wait_ready(NPCX_FLASH_ABORT_TIMEOUT);
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}
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int flash_physical_write(uint32_t offset, uint32_t size, const uint8_t *data)
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{
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int status;
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uint32_t trunk_start = (offset + 0xff) & ~0xff;
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/* write head */
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uint32_t dest_addr = offset;
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uint32_t write_len = ((trunk_start - offset) > size) ? size : (trunk_start - offset);
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if (write_len) {
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status = flash_program_write(dest_addr, write_len, data);
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if (status != NPCX_FLASH_STATUS_OK)
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return status;
|
||||
data += write_len;
|
||||
}
|
||||
|
||||
dest_addr = trunk_start;
|
||||
size -= write_len;
|
||||
|
||||
/* write remaining data*/
|
||||
while (size > 0) {
|
||||
write_len = (size > NPCX_FLASH_WRITE_SIZE) ?
|
||||
NPCX_FLASH_WRITE_SIZE : size;
|
||||
|
||||
status = flash_program_write(dest_addr, write_len, data);
|
||||
if (status != NPCX_FLASH_STATUS_OK)
|
||||
return status;
|
||||
|
||||
data += write_len;
|
||||
dest_addr += write_len;
|
||||
size -= write_len;
|
||||
}
|
||||
|
||||
return NPCX_FLASH_STATUS_OK;
|
||||
}
|
||||
|
||||
int flash_physical_erase(uint32_t offset, uint32_t size)
|
||||
{
|
||||
/* Alignment has been checked in upper layer */
|
||||
for (; size > 0; size -= NPCX_FLASH_ERASE_SIZE,
|
||||
offset += NPCX_FLASH_ERASE_SIZE) {
|
||||
/* Enable write */
|
||||
int status = flash_write_enable();
|
||||
if (status != NPCX_FLASH_STATUS_OK)
|
||||
return status;
|
||||
|
||||
/* Set erase address */
|
||||
flash_set_address(offset);
|
||||
/* Start erase */
|
||||
flash_execute_cmd(NPCX_CMD_SECTOR_ERASE, NPCX_MASK_CMD_ADR);
|
||||
/* Wait erase completed */
|
||||
status = flash_wait_ready(NPCX_FLASH_ABORT_TIMEOUT);
|
||||
if (status != NPCX_FLASH_STATUS_OK)
|
||||
return status;
|
||||
}
|
||||
|
||||
return NPCX_FLASH_STATUS_OK;
|
||||
}
|
||||
|
||||
int flash_physical_erase_all(void)
|
||||
{
|
||||
/* Enable write */
|
||||
int status = flash_write_enable();
|
||||
if (status != NPCX_FLASH_STATUS_OK)
|
||||
return status;
|
||||
|
||||
/* Start erase */
|
||||
flash_execute_cmd(NPCX_CMD_CHIP_ERASE, NPCX_MASK_CMD_ONLY);
|
||||
|
||||
/* Wait erase completed */
|
||||
status = flash_wait_ready(NPCX_FLASH_ABORT_TIMEOUT);
|
||||
if (status != NPCX_FLASH_STATUS_OK)
|
||||
return status;
|
||||
|
||||
return NPCX_FLASH_STATUS_OK;
|
||||
}
|
||||
|
||||
int flash_physical_clear_stsreg(void)
|
||||
{
|
||||
/* Enable write */
|
||||
int status = flash_write_enable();
|
||||
if (status != NPCX_FLASH_STATUS_OK)
|
||||
return status;
|
||||
|
||||
NPCX_UMA_DB0 = 0x0;
|
||||
NPCX_UMA_DB1 = 0x0;
|
||||
|
||||
/* Write status register 1/2 */
|
||||
flash_execute_cmd(NPCX_CMD_WRITE_STATUS_REG, NPCX_MASK_CMD_WR_2BYTE);
|
||||
|
||||
/* Wait writing completed */
|
||||
status = flash_wait_ready(NPCX_FLASH_ABORT_TIMEOUT);
|
||||
if (status != NPCX_FLASH_STATUS_OK)
|
||||
return status;
|
||||
|
||||
/* Read status register 1/2 for checking */
|
||||
flash_execute_cmd(NPCX_CMD_READ_STATUS_REG, NPCX_MASK_CMD_RD_1BYTE);
|
||||
if (NPCX_UMA_DB0 != 0x00)
|
||||
return NPCX_FLASH_STATUS_FAILED;
|
||||
flash_execute_cmd(NPCX_CMD_READ_STATUS_REG2, NPCX_MASK_CMD_RD_1BYTE);
|
||||
if (NPCX_UMA_DB0 != 0x00)
|
||||
return NPCX_FLASH_STATUS_FAILED;
|
||||
|
||||
return NPCX_FLASH_STATUS_OK;
|
||||
}
|
||||
|
||||
int flash_get_id(uint32_t *id)
|
||||
{
|
||||
flash_execute_cmd(NPCX_CMD_READ_ID, NPCX_MASK_CMD_RD_3BYTE);
|
||||
*id = NPCX_UMA_DB0 << 16 | NPCX_UMA_DB1 << 8 | NPCX_UMA_DB2;
|
||||
|
||||
return NPCX_FLASH_STATUS_OK;
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* flash loader function
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t flashloader_init(struct npcx_flash_params *params)
|
||||
{
|
||||
/* Initialize params buffers */
|
||||
memset(params, 0, sizeof(struct npcx_flash_params));
|
||||
|
||||
return NPCX_FLASH_STATUS_OK;
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Functions
|
||||
*----------------------------------------------------------------------------*/
|
||||
/* flashloader parameter structure */
|
||||
__attribute__ ((section(".buffers.g_cfg")))
|
||||
volatile struct npcx_flash_params g_cfg;
|
||||
/* data buffer */
|
||||
__attribute__ ((section(".buffers.g_buf")))
|
||||
uint8_t g_buf[NPCX_FLASH_LOADER_BUFFER_SIZE];
|
||||
|
||||
int main(void)
|
||||
{
|
||||
uint32_t id;
|
||||
|
||||
/* set buffer */
|
||||
flashloader_init((struct npcx_flash_params *)&g_cfg);
|
||||
|
||||
/* Avoid F_CS0 toggles while programming the internal flash. */
|
||||
NPCX_SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_NO_F_SPI);
|
||||
|
||||
/* clear flash status registers */
|
||||
int status = flash_physical_clear_stsreg();
|
||||
if (status != NPCX_FLASH_STATUS_OK) {
|
||||
while (1)
|
||||
g_cfg.sync = status;
|
||||
}
|
||||
|
||||
while (1) {
|
||||
/* wait command*/
|
||||
while (g_cfg.sync == NPCX_FLASH_LOADER_WAIT)
|
||||
;
|
||||
|
||||
/* command handler */
|
||||
switch (g_cfg.cmd) {
|
||||
case NPCX_FLASH_CMD_GET_FLASH_ID:
|
||||
status = flash_get_id(&id);
|
||||
if (status == NPCX_FLASH_STATUS_OK) {
|
||||
g_buf[0] = id & 0xff;
|
||||
g_buf[1] = (id >> 8) & 0xff;
|
||||
g_buf[2] = (id >> 16) & 0xff;
|
||||
g_buf[3] = 0x00;
|
||||
}
|
||||
break;
|
||||
case NPCX_FLASH_CMD_ERASE_SECTORS:
|
||||
status = flash_physical_erase(g_cfg.addr, g_cfg.len);
|
||||
break;
|
||||
case NPCX_FLASH_CMD_ERASE_ALL:
|
||||
status = flash_physical_erase_all();
|
||||
break;
|
||||
case NPCX_FLASH_CMD_PROGRAM:
|
||||
status = flash_physical_write(g_cfg.addr,
|
||||
g_cfg.len,
|
||||
g_buf);
|
||||
break;
|
||||
default:
|
||||
status = NPCX_FLASH_STATUS_FAILED_UNKNOWN_COMMAND;
|
||||
break;
|
||||
}
|
||||
|
||||
/* clear & set result for next command */
|
||||
if (status != NPCX_FLASH_STATUS_OK) {
|
||||
g_cfg.sync = status;
|
||||
while (1)
|
||||
;
|
||||
} else {
|
||||
g_cfg.sync = NPCX_FLASH_LOADER_WAIT;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
__attribute__ ((section(".stack")))
|
||||
__attribute__ ((used))
|
||||
static uint32_t stack[NPCX_FLASH_LOADER_STACK_SIZE / 4];
|
||||
extern uint32_t _estack;
|
||||
extern uint32_t _bss;
|
||||
extern uint32_t _ebss;
|
||||
|
||||
__attribute__ ((section(".entry")))
|
||||
void entry(void)
|
||||
{
|
||||
/* set sp from end of stack */
|
||||
__asm(" ldr sp, =_estack - 4");
|
||||
|
||||
main();
|
||||
|
||||
__asm(" bkpt #0x00");
|
||||
}
|
||||
@@ -0,0 +1,179 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
/*
|
||||
* Copyright (C) 2020 by Nuvoton Technology Corporation
|
||||
* Mulin Chao <mlchao@nuvoton.com>
|
||||
* Wealian Liao <WHLIAO@nuvoton.com>
|
||||
*/
|
||||
|
||||
#ifndef OPENOCD_LOADERS_FLASH_NPCX_NPCX_FLASH_H
|
||||
#define OPENOCD_LOADERS_FLASH_NPCX_NPCX_FLASH_H
|
||||
|
||||
#include "npcx_flash_config.h"
|
||||
|
||||
/* Bit functions */
|
||||
#define NPCX_SET_BIT(reg, bit) ((reg) |= (0x1 << (bit)))
|
||||
#define NPCX_CLEAR_BIT(reg, bit) ((reg) &= (~(0x1 << (bit))))
|
||||
#define NPCX_IS_BIT_SET(reg, bit) (((reg) >> (bit)) & (0x1))
|
||||
|
||||
/* Field functions */
|
||||
#define NPCX_GET_POS_FIELD(pos, size) (pos)
|
||||
#define NPCX_GET_SIZE_FIELD(pos, size) (size)
|
||||
#define NPCX_FIELD_POS(field) NPCX_GET_POS_##field
|
||||
#define NPCX_FIELD_SIZE(field) NPCX_GET_SIZE_##field
|
||||
/* Read field functions */
|
||||
#define NPCX_GET_FIELD(reg, field) \
|
||||
_NPCX_GET_FIELD_((reg), NPCX_FIELD_POS(field), NPCX_FIELD_SIZE(field))
|
||||
#define _NPCX_GET_FIELD_(reg, f_pos, f_size) \
|
||||
(((reg) >> (f_pos)) & ((1 << (f_size)) - 1))
|
||||
/* Write field functions */
|
||||
#define NPCX_SET_FIELD(reg, field, value) \
|
||||
_NPCX_SET_FIELD_((reg), NPCX_FIELD_POS(field), NPCX_FIELD_SIZE(field), (value))
|
||||
#define _NPCX_SET_FIELD_(reg, f_pos, f_size, value) \
|
||||
((reg) = ((reg) & (~(((1 << (f_size)) - 1) << (f_pos)))) | ((value) << (f_pos)))
|
||||
|
||||
/* Register definitions */
|
||||
#define NPCX_REG32_ADDR(addr) ((volatile uint32_t *)(addr))
|
||||
#define NPCX_REG16_ADDR(addr) ((volatile uint16_t *)(addr))
|
||||
#define NPCX_REG8_ADDR(addr) ((volatile uint8_t *)(addr))
|
||||
|
||||
#define NPCX_HW_BYTE(addr) (*NPCX_REG8_ADDR(addr))
|
||||
#define NPCX_HW_WORD(addr) (*NPCX_REG16_ADDR(addr))
|
||||
#define NPCX_HW_DWORD(addr) (*NPCX_REG32_ADDR(addr))
|
||||
|
||||
/* Devalt */
|
||||
#define NPCX_SCFG_BASE_ADDR 0x400C3000
|
||||
#define NPCX_DEVCNT NPCX_HW_BYTE(NPCX_SCFG_BASE_ADDR + 0x000)
|
||||
#define NPCX_DEVALT(n) NPCX_HW_BYTE(NPCX_SCFG_BASE_ADDR + 0x010 + (n))
|
||||
|
||||
#define NPCX_DEVCNT_HIF_TYP_SEL_FIELD FIELD(2, 2)
|
||||
#define NPCX_DEVCNT_JEN0_HEN 4
|
||||
#define NPCX_DEVCNT_JEN1_HEN 5
|
||||
#define NPCX_DEVCNT_F_SPI_TRIS 6
|
||||
|
||||
/* Pin-mux for SPI/FIU */
|
||||
#define NPCX_DEVALT0_SPIP_SL 0
|
||||
#define NPCX_DEVALT0_GPIO_NO_SPIP 3
|
||||
#define NPCX_DEVALT0_F_SPI_CS1_2 4
|
||||
#define NPCX_DEVALT0_F_SPI_CS1_1 5
|
||||
#define NPCX_DEVALT0_F_SPI_QUAD 6
|
||||
#define NPCX_DEVALT0_NO_F_SPI 7
|
||||
|
||||
/* Flash Interface Unit (FIU) registers */
|
||||
#define NPCX_FIU_BASE_ADDR 0x40020000
|
||||
#define NPCX_FIU_CFG NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x000)
|
||||
#define NPCX_BURST_CFG NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x001)
|
||||
#define NPCX_RESP_CFG NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x002)
|
||||
#define NPCX_SPI_FL_CFG NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x014)
|
||||
#define NPCX_UMA_CODE NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x016)
|
||||
#define NPCX_UMA_AB0 NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x017)
|
||||
#define NPCX_UMA_AB1 NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x018)
|
||||
#define NPCX_UMA_AB2 NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x019)
|
||||
#define NPCX_UMA_DB0 NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x01A)
|
||||
#define NPCX_UMA_DB1 NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x01B)
|
||||
#define NPCX_UMA_DB2 NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x01C)
|
||||
#define NPCX_UMA_DB3 NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x01D)
|
||||
#define NPCX_UMA_CTS NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x01E)
|
||||
#define NPCX_UMA_ECTS NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x01F)
|
||||
#define NPCX_UMA_DB0_3 NPCX_HW_DWORD(NPCX_FIU_BASE_ADDR + 0x020)
|
||||
#define NPCX_FIU_RD_CMD NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x030)
|
||||
#define NPCX_FIU_DMM_CYC NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x032)
|
||||
#define NPCX_FIU_EXT_CFG NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x033)
|
||||
#define NPCX_FIU_UMA_AB0_3 NPCX_HW_DWORD(NPCX_FIU_BASE_ADDR + 0x034)
|
||||
|
||||
/* FIU register fields */
|
||||
#define NPCX_RESP_CFG_IAD_EN 0
|
||||
#define NPCX_RESP_CFG_DEV_SIZE_EX 2
|
||||
#define NPCX_UMA_CTS_A_SIZE 3
|
||||
#define NPCX_UMA_CTS_C_SIZE 4
|
||||
#define NPCX_UMA_CTS_RD_WR 5
|
||||
#define NPCX_UMA_CTS_DEV_NUM 6
|
||||
#define NPCX_UMA_CTS_EXEC_DONE 7
|
||||
#define NPCX_UMA_ECTS_SW_CS0 0
|
||||
#define NPCX_UMA_ECTS_SW_CS1 1
|
||||
#define NPCX_UMA_ECTS_SEC_CS 2
|
||||
#define NPCX_UMA_ECTS_UMA_LOCK 3
|
||||
|
||||
/* Flash UMA commands for npcx internal SPI flash */
|
||||
#define NPCX_CMD_READ_ID 0x9F
|
||||
#define NPCX_CMD_READ_MAN_DEV_ID 0x90
|
||||
#define NPCX_CMD_WRITE_EN 0x06
|
||||
#define NPCX_CMD_WRITE_STATUS 0x50
|
||||
#define NPCX_CMD_READ_STATUS_REG 0x05
|
||||
#define NPCX_CMD_READ_STATUS_REG2 0x35
|
||||
#define NPCX_CMD_WRITE_STATUS_REG 0x01
|
||||
#define NPCX_CMD_FLASH_PROGRAM 0x02
|
||||
#define NPCX_CMD_SECTOR_ERASE 0x20
|
||||
#define NPCX_CMD_PROGRAM_UINT_SIZE 0x08
|
||||
#define NPCX_CMD_PAGE_SIZE 0x00
|
||||
#define NPCX_CMD_READ_ID_TYPE 0x47
|
||||
#define NPCX_CMD_FAST_READ 0x0B
|
||||
#define NPCX_CMD_CHIP_ERASE 0xC7
|
||||
|
||||
/*
|
||||
* Status registers for SPI flash
|
||||
*/
|
||||
#define NPCX_SPI_FLASH_SR2_SUS (1 << 7)
|
||||
#define NPCX_SPI_FLASH_SR2_CMP (1 << 6)
|
||||
#define NPCX_SPI_FLASH_SR2_LB3 (1 << 5)
|
||||
#define NPCX_SPI_FLASH_SR2_LB2 (1 << 4)
|
||||
#define NPCX_SPI_FLASH_SR2_LB1 (1 << 3)
|
||||
#define NPCX_SPI_FLASH_SR2_QE (1 << 1)
|
||||
#define NPCX_SPI_FLASH_SR2_SRP1 (1 << 0)
|
||||
#define NPCX_SPI_FLASH_SR1_SRP0 (1 << 7)
|
||||
#define NPCX_SPI_FLASH_SR1_SEC (1 << 6)
|
||||
#define NPCX_SPI_FLASH_SR1_TB (1 << 5)
|
||||
#define NPCX_SPI_FLASH_SR1_BP2 (1 << 4)
|
||||
#define NPCX_SPI_FLASH_SR1_BP1 (1 << 3)
|
||||
#define NPCX_SPI_FLASH_SR1_BP0 (1 << 2)
|
||||
#define NPCX_SPI_FLASH_SR1_WEL (1 << 1)
|
||||
#define NPCX_SPI_FLASH_SR1_BUSY (1 << 0)
|
||||
|
||||
#define NPCX_MASK_CMD_ONLY (0xC0)
|
||||
#define NPCX_MASK_CMD_ADR (0xC0 | 0x08)
|
||||
#define NPCX_MASK_CMD_ADR_WR (0xC0 | 0x20 | 0x08 | 0x01)
|
||||
#define NPCX_MASK_RD_1BYTE (0xC0 | 0x10 | 0x01)
|
||||
#define NPCX_MASK_RD_2BYTE (0xC0 | 0x10 | 0x02)
|
||||
#define NPCX_MASK_RD_3BYTE (0xC0 | 0x10 | 0x03)
|
||||
#define NPCX_MASK_RD_4BYTE (0xC0 | 0x10 | 0x04)
|
||||
#define NPCX_MASK_CMD_RD_1BYTE (0xC0 | 0x01)
|
||||
#define NPCX_MASK_CMD_RD_2BYTE (0xC0 | 0x02)
|
||||
#define NPCX_MASK_CMD_RD_3BYTE (0xC0 | 0x03)
|
||||
#define NPCX_MASK_CMD_RD_4BYTE (0xC0 | 0x04)
|
||||
#define NPCX_MASK_CMD_WR_ONLY (0xC0 | 0x20)
|
||||
#define NPCX_MASK_CMD_WR_1BYTE (0xC0 | 0x20 | 0x10 | 0x01)
|
||||
#define NPCX_MASK_CMD_WR_2BYTE (0xC0 | 0x20 | 0x10 | 0x02)
|
||||
#define NPCX_MASK_CMD_WR_ADR (0xC0 | 0x20 | 0x08)
|
||||
|
||||
/* Flash loader parameters */
|
||||
struct __attribute__((__packed__)) npcx_flash_params {
|
||||
uint32_t addr; /* Address in flash */
|
||||
uint32_t len; /* Number of bytes */
|
||||
uint32_t cmd; /* Command */
|
||||
uint32_t sync; /* Handshake signal */
|
||||
};
|
||||
|
||||
/* Flash trigger signal */
|
||||
enum npcx_flash_handshake {
|
||||
NPCX_FLASH_LOADER_WAIT = 0x0, /* Idle */
|
||||
NPCX_FLASH_LOADER_EXECUTE = 0xFFFFFFFF /* Execute Command */
|
||||
};
|
||||
|
||||
/* Flash loader command */
|
||||
enum npcx_flash_commands {
|
||||
NPCX_FLASH_CMD_NO_ACTION = 0, /* No action, default value */
|
||||
NPCX_FLASH_CMD_GET_FLASH_ID, /* Get the internal flash ID */
|
||||
NPCX_FLASH_CMD_ERASE_SECTORS, /* Erase unprotected sectors */
|
||||
NPCX_FLASH_CMD_ERASE_ALL, /* Erase all */
|
||||
NPCX_FLASH_CMD_PROGRAM, /* Program data */
|
||||
};
|
||||
|
||||
/* Status */
|
||||
enum npcx_flash_status {
|
||||
NPCX_FLASH_STATUS_OK = 0,
|
||||
NPCX_FLASH_STATUS_FAILED_UNKNOWN_COMMAND,
|
||||
NPCX_FLASH_STATUS_FAILED,
|
||||
NPCX_FLASH_STATUS_FAILED_TIMEOUT,
|
||||
};
|
||||
|
||||
#endif /* OPENOCD_LOADERS_FLASH_NPCX_NPCX_FLASH_H */
|
||||
@@ -0,0 +1,58 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include "npcx_flash_config.h"
|
||||
|
||||
/* Application memory map */
|
||||
MEMORY {
|
||||
/* buffer + parameters */
|
||||
BUFFER (RWX) : ORIGIN = NPCX_FLASH_LOADER_PARAMS_ADDR,
|
||||
LENGTH = NPCX_FLASH_LOADER_PARAMS_SIZE + NPCX_FLASH_LOADER_BUFFER_SIZE
|
||||
|
||||
PROGRAM (RWX) : ORIGIN = NPCX_FLASH_LOADER_PROGRAM_ADDR,
|
||||
LENGTH = NPCX_FLASH_LOADER_PROGRAM_SIZE
|
||||
}
|
||||
|
||||
/* Sections used for flashing */
|
||||
SECTIONS
|
||||
{
|
||||
.buffers (NOLOAD) :
|
||||
{
|
||||
_buffers = .;
|
||||
*(.buffers.g_cfg)
|
||||
*(.buffers.g_buf)
|
||||
*(.buffers*)
|
||||
_ebuffers = .;
|
||||
} > BUFFER
|
||||
|
||||
.text :
|
||||
{
|
||||
_text = .;
|
||||
*(.entry*)
|
||||
*(.text*)
|
||||
_etext = .;
|
||||
} > PROGRAM
|
||||
|
||||
.data :
|
||||
{ _data = .;
|
||||
*(.rodata*)
|
||||
*(.data*)
|
||||
_edata = .;
|
||||
} > PROGRAM
|
||||
|
||||
.bss :
|
||||
{
|
||||
__bss_start__ = .;
|
||||
_bss = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
_ebss = .;
|
||||
__bss_end__ = .;
|
||||
} > PROGRAM
|
||||
|
||||
.stack (NOLOAD) :
|
||||
{
|
||||
_stack = .;
|
||||
*(.stack*)
|
||||
_estack = .;
|
||||
} > PROGRAM
|
||||
}
|
||||
@@ -0,0 +1,31 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
/*
|
||||
* Copyright (C) 2021 by Nuvoton Technology Corporation
|
||||
* Mulin Chao <mlchao@nuvoton.com>
|
||||
* Wealian Liao <WHLIAO@nuvoton.com>
|
||||
*/
|
||||
|
||||
#ifndef OPENOCD_LOADERS_FLASH_NPCX_NPCX_FLASH_CONFIG_H
|
||||
#define OPENOCD_LOADERS_FLASH_NPCX_NPCX_FLASH_CONFIG_H
|
||||
|
||||
#define NPCX_FLASH_ABORT_TIMEOUT 0xFFFFFF
|
||||
|
||||
/* NPCX chip information */
|
||||
#define NPCX_FLASH_WRITE_SIZE 256L /* One page size for write */
|
||||
#define NPCX_FLASH_ERASE_SIZE 0x1000
|
||||
|
||||
/* NPCX flash loader information */
|
||||
#define NPCX_FLASH_LOADER_WORKING_ADDR 0x200C0000
|
||||
#define NPCX_FLASH_LOADER_PARAMS_ADDR NPCX_FLASH_LOADER_WORKING_ADDR
|
||||
#define NPCX_FLASH_LOADER_PARAMS_SIZE 16
|
||||
#define NPCX_FLASH_LOADER_BUFFER_ADDR (NPCX_FLASH_LOADER_PARAMS_ADDR + NPCX_FLASH_LOADER_PARAMS_SIZE)
|
||||
#define NPCX_FLASH_LOADER_BUFFER_SIZE NPCX_FLASH_ERASE_SIZE
|
||||
#define NPCX_FLASH_LOADER_PROGRAM_ADDR (NPCX_FLASH_LOADER_BUFFER_ADDR + NPCX_FLASH_LOADER_BUFFER_SIZE)
|
||||
#define NPCX_FLASH_LOADER_PROGRAM_SIZE 0x1000
|
||||
|
||||
/* Stack size in byte. 4 byte size alignment */
|
||||
#define NPCX_FLASH_LOADER_STACK_SIZE 400
|
||||
|
||||
|
||||
#endif /* OPENOCD_LOADERS_FLASH_NPCX_NPCX_FLASH_CONFIG_H */
|
||||
Reference in New Issue
Block a user