forked from auracaster/openocd
nrf5: Refresh the watchdog while flashing
If watchdog is enabled, there's no way we can disable it while the flashing firmware is running. (Halt disables it, but software reset doesn't.) So let's have the flashing firmware refresh the watchdog regularly, in case it has been enabled by previously running software. Failure to do so could lead to a watchdog reset in the middle of the chip bieng programmed. Change-Id: I79d41593948aae0080480e891552e1c2ee3ccbd0 Signed-off-by: Aurélien Martin <martaurel@gmail.com> Reviewed-on: http://openocd.zylin.com/5266 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit is contained in:
committed by
Tomas Vanek
parent
65d8fdf0d1
commit
3c8aa12859
@@ -27,12 +27,15 @@
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* r1 = buffer start
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* r2 = buffer end
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* r3 = target address
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* r6 = watchdog refresh value
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* r7 = watchdog refresh register address
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*/
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.thumb_func
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.global _start
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_start:
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wait_fifo:
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str r6, [r7, #0]
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ldr r5, [r1, #0]
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cmp r5, #0
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beq.n exit
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@@ -1,3 +1,4 @@
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/* Autogenerated with ../../../../src/helper/bin2char.sh */
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0x0d,0x68,0x00,0x2d,0x0b,0xd0,0x4c,0x68,0xac,0x42,0xf9,0xd0,0x20,0xcc,0x20,0xc3,
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0x94,0x42,0x01,0xd3,0x0c,0x46,0x08,0x34,0x4c,0x60,0x04,0x38,0xf0,0xd1,0x00,0xbe,
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0x3e,0x60,0x0d,0x68,0x00,0x2d,0x0b,0xd0,0x4c,0x68,0xac,0x42,0xf8,0xd0,0x20,0xcc,
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0x20,0xc3,0x94,0x42,0x01,0xd3,0x0c,0x46,0x08,0x34,0x4c,0x60,0x04,0x38,0xef,0xd1,
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0x00,0xbe,
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