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target/arm_adi_v5: extend apcsw command to accept arbitrary bits

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apcsw command was limited to SPROT bit only.

Now user can manipulate any bit except size and addrinc fields.
Can be used e.g. to set bus signal 'cacheable' on Cortex-M7

Change-Id: Ia1c22b208e46d1653136f6faa5a7aaab036de7aa
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4431
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
This commit is contained in:
Tomas Vanek
2018-02-23 00:03:20 +01:00
committed by Matthias Welwarsky
parent 2e2bb14b27
commit 414213a5ea
4 changed files with 75 additions and 21 deletions
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9
src/target/arm_adi_v5.h
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@@ -112,13 +112,16 @@
#define CSW_ADDRINC_PACKED (2UL << 4)
#define CSW_DEVICE_EN (1UL << 6)
#define CSW_TRIN_PROG (1UL << 7)
/* all fields in bits 12 and above are implementation-defined! */
#define CSW_SPIDEN (1UL << 23)
/* 30:24 - implementation-defined! */
#define CSW_HPROT (1UL << 25) /* ? */
#define CSW_MASTER_DEBUG (1UL << 29) /* ? */
#define CSW_HPROT1 (1UL << 25) /* AHB: Privileged */
#define CSW_MASTER_DEBUG (1UL << 29) /* AHB: set HMASTER signals to AHB-AP ID */
#define CSW_SPROT (1UL << 30)
#define CSW_DBGSWENABLE (1UL << 31)
/* initial value of csw_default used for MEM-AP transfers */
#define CSW_DEFAULT (CSW_HPROT1 | CSW_MASTER_DEBUG | CSW_DBGSWENABLE)
/* Fields of the MEM-AP's IDR register */
#define IDR_REV (0xFUL << 28)
#define IDR_JEP106 (0x7FFUL << 17)