forked from auracaster/openocd
target: fix minor typos and duplicated words
Change-Id: I8deb0017dc66a243e3dd51e285aa086db500decd Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5766 Tested-by: jenkins
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@@ -113,7 +113,7 @@ static int cortexm_dap_write_coreregister_u32(struct target *target,
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return retval;
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if (target->dbg_msg_enabled) {
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/* restore DCB_DCRDR - this needs to be in a seperate
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/* restore DCB_DCRDR - this needs to be in a separate
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* transaction otherwise the emulated DCC channel breaks */
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if (retval == ERROR_OK)
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retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
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@@ -951,7 +951,7 @@ static int cortex_m_step(struct target *target, int current,
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* just step over the instruction with interrupts disabled.
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*
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* The documentation has no information about this, it was found by observation
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* on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 dosen't seem to
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* on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 doesn't seem to
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* suffer from this problem.
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*
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* To add some confusion: pc_value has bit 0 always set, while the breakpoint
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