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esirisc: support eSi-RISC targets

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eSi-RISC is a highly configurable microprocessor architecture for
embedded systems provided by EnSilica. This patch adds support for
32-bit targets and also includes an internal flash driver and
uC/OS-III RTOS support. This is a non-traditional target and required
a number of additional changes to support non-linear register numbers
and the 'p' packet in RTOS support for proper integration into
EnSilica's GDB port.

Change-Id: I59d5c40b3bb2ace1b1a01b2538bfab211adf113f
Signed-off-by: Steven Stallion <stallion@squareup.com>
Reviewed-on: http://openocd.zylin.com/4660
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
This commit is contained in:
Steven Stallion
2018-08-28 17:18:01 -07:00
committed by Matthias Welwarsky
parent e72b2601e7
commit 4ab75a3634
17 changed files with 3496 additions and 9 deletions
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30
src/rtos/rtos_ucos_iii_stackings.c
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@@ -24,6 +24,7 @@
#include <rtos/rtos.h>
#include <rtos/rtos_standard_stackings.h>
#include <target/armv7m.h>
#include <target/esirisc.h>
static const struct stack_register_offset rtos_uCOS_III_Cortex_M_stack_offsets[] = {
{ ARMV7M_R0, 0x20, 32 }, /* r0 */
@@ -45,6 +46,27 @@ static const struct stack_register_offset rtos_uCOS_III_Cortex_M_stack_offsets[]
{ ARMV7M_xPSR, 0x3c, 32 }, /* xPSR */
};
static const struct stack_register_offset rtos_uCOS_III_eSi_RISC_stack_offsets[] = {
{ ESIRISC_SP, -2, 32 }, /* sp */
{ ESIRISC_RA, 0x48, 32 }, /* ra */
{ ESIRISC_R2, 0x44, 32 }, /* r2 */
{ ESIRISC_R3, 0x40, 32 }, /* r3 */
{ ESIRISC_R4, 0x3c, 32 }, /* r4 */
{ ESIRISC_R5, 0x38, 32 }, /* r5 */
{ ESIRISC_R6, 0x34, 32 }, /* r6 */
{ ESIRISC_R7, 0x30, 32 }, /* r7 */
{ ESIRISC_R8, 0x2c, 32 }, /* r8 */
{ ESIRISC_R9, 0x28, 32 }, /* r9 */
{ ESIRISC_R10, 0x24, 32 }, /* r10 */
{ ESIRISC_R11, 0x20, 32 }, /* r11 */
{ ESIRISC_R12, 0x1c, 32 }, /* r12 */
{ ESIRISC_R13, 0x18, 32 }, /* r13 */
{ ESIRISC_R14, 0x14, 32 }, /* r14 */
{ ESIRISC_R15, 0x10, 32 }, /* r15 */
{ ESIRISC_PC, 0x04, 32 }, /* PC */
{ ESIRISC_CAS, 0x08, 32 }, /* CAS */
};
const struct rtos_register_stacking rtos_uCOS_III_Cortex_M_stacking = {
0x40, /* stack_registers_size */
-1, /* stack_growth_direction */
@@ -52,3 +74,11 @@ const struct rtos_register_stacking rtos_uCOS_III_Cortex_M_stacking = {
rtos_generic_stack_align8, /* stack_alignment */
rtos_uCOS_III_Cortex_M_stack_offsets /* register_offsets */
};
const struct rtos_register_stacking rtos_uCOS_III_eSi_RISC_stacking = {
0x4c, /* stack_registers_size */
-1, /* stack_growth_direction */
ARRAY_SIZE(rtos_uCOS_III_eSi_RISC_stack_offsets), /* num_output_registers */
NULL, /* stack_alignment */
rtos_uCOS_III_eSi_RISC_stack_offsets /* register_offsets */
};

1
src/rtos/rtos_ucos_iii_stackings.h
View File

@@ -26,5 +26,6 @@
#include <rtos/rtos.h>
extern const struct rtos_register_stacking rtos_uCOS_III_Cortex_M_stacking;
extern const struct rtos_register_stacking rtos_uCOS_III_eSi_RISC_stacking;
#endif /* OPENOCD_RTOS_RTOS_UCOS_III_STACKINGS_H */

14
src/rtos/uCOS-III.c
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@@ -68,6 +68,20 @@ static const struct uCOS_III_params uCOS_III_params_list[] = {
&rtos_uCOS_III_Cortex_M_stacking, /* stacking_info */
0, /* num_threads */
},
{
"esirisc", /* target_name */
sizeof(uint32_t), /* pointer_width */
0, /* thread_stack_offset */
0, /* thread_name_offset */
0, /* thread_state_offset */
0, /* thread_priority_offset */
0, /* thread_prev_offset */
0, /* thread_next_offset */
false, /* thread_offsets_updated */
1, /* threadid_start */
&rtos_uCOS_III_eSi_RISC_stacking, /* stacking_info */
0, /* num_threads */
},
};
static const char * const uCOS_III_symbol_list[] = {