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esirisc: support eSi-RISC targets

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eSi-RISC is a highly configurable microprocessor architecture for
embedded systems provided by EnSilica. This patch adds support for
32-bit targets and also includes an internal flash driver and
uC/OS-III RTOS support. This is a non-traditional target and required
a number of additional changes to support non-linear register numbers
and the 'p' packet in RTOS support for proper integration into
EnSilica's GDB port.

Change-Id: I59d5c40b3bb2ace1b1a01b2538bfab211adf113f
Signed-off-by: Steven Stallion <stallion@squareup.com>
Reviewed-on: http://openocd.zylin.com/4660
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
This commit is contained in:
Steven Stallion
2018-08-28 17:18:01 -07:00
committed by Matthias Welwarsky
parent e72b2601e7
commit 4ab75a3634
17 changed files with 3496 additions and 9 deletions
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1
src/rtos/rtos_ucos_iii_stackings.h
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@@ -26,5 +26,6 @@
#include <rtos/rtos.h>
extern const struct rtos_register_stacking rtos_uCOS_III_Cortex_M_stacking;
extern const struct rtos_register_stacking rtos_uCOS_III_eSi_RISC_stacking;
#endif /* OPENOCD_RTOS_RTOS_UCOS_III_STACKINGS_H */