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esirisc: support eSi-RISC targets

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eSi-RISC is a highly configurable microprocessor architecture for
embedded systems provided by EnSilica. This patch adds support for
32-bit targets and also includes an internal flash driver and
uC/OS-III RTOS support. This is a non-traditional target and required
a number of additional changes to support non-linear register numbers
and the 'p' packet in RTOS support for proper integration into
EnSilica's GDB port.

Change-Id: I59d5c40b3bb2ace1b1a01b2538bfab211adf113f
Signed-off-by: Steven Stallion <stallion@squareup.com>
Reviewed-on: http://openocd.zylin.com/4660
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
This commit is contained in:
Steven Stallion
2018-08-28 17:18:01 -07:00
committed by Matthias Welwarsky
parent e72b2601e7
commit 4ab75a3634
17 changed files with 3496 additions and 9 deletions
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10
src/target/Makefile.am
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@@ -23,6 +23,7 @@ noinst_LTLIBRARIES += %D%/libtarget.la
$(NDS32_SRC) \
$(STM8_SRC) \
$(INTEL_IA32_SRC) \
$(ESIRISC_SRC) \
%D%/avrt.c \
%D%/dsp563xx.c \
%D%/dsp563xx_once.c \
@@ -139,6 +140,10 @@ INTEL_IA32_SRC = \
%D%/lakemont.c \
%D%/x86_32_common.c
ESIRISC_SRC = \
%D%/esirisc.c \
%D%/esirisc_jtag.c
%C%_libtarget_la_SOURCES += \
%D%/algorithm.h \
%D%/arm.h \
@@ -218,7 +223,10 @@ INTEL_IA32_SRC = \
%D%/stm8.h \
%D%/lakemont.h \
%D%/x86_32_common.h \
%D%/arm_cti.h
%D%/arm_cti.h \
%D%/esirisc.h \
%D%/esirisc_jtag.h \
%D%/esirisc_regs.h
include %D%/openrisc/Makefile.am
include %D%/riscv/Makefile.am

1787
src/target/esirisc.c Normal file
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129
src/target/esirisc.h Normal file
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@@ -0,0 +1,129 @@
/***************************************************************************
* Copyright (C) 2018 by Square, Inc. *
* Steven Stallion <stallion@squareup.com> *
* James Zhao <hjz@squareup.com> *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#ifndef OPENOCD_TARGET_ESIRISC_H
#define OPENOCD_TARGET_ESIRISC_H
#include <target/breakpoints.h>
#include <target/register.h>
#include <target/target.h>
#include "esirisc_jtag.h"
#include "esirisc_regs.h"
#define MAX_BREAKPOINTS 8
#define MAX_WATCHPOINTS 8
/* Exception IDs */
#define EID_RESET 0x00
#define EID_HARDWARE_FAILURE 0x01
#define EID_NMI 0x02
#define EID_INST_BREAKPOINT 0x03
#define EID_DATA_BREAKPOINT 0x04
#define EID_UNSUPPORTED 0x05
#define EID_PRIVILEGE_VIOLATION 0x06
#define EID_INST_BUS_ERROR 0x07
#define EID_DATA_BUS_ERROR 0x08
#define EID_ALIGNMENT_ERROR 0x09
#define EID_ARITHMETIC_ERROR 0x0a
#define EID_SYSTEM_CALL 0x0b
#define EID_MEMORY_MANAGEMENT 0x0c
#define EID_UNRECOVERABLE 0x0d
#define EID_INTERRUPTn 0x20
/* Exception Entry Points */
#define ENTRY_RESET 0x00
#define ENTRY_UNRECOVERABLE 0x01
#define ENTRY_HARDWARE_FAILURE 0x02
#define ENTRY_RUNTIME 0x03
#define ENTRY_MEMORY 0x04
#define ENTRY_SYSCALL 0x05
#define ENTRY_DEBUG 0x06
#define ENTRY_NMI 0x07
#define ENTRY_INTERRUPTn 0x08
/* Hardware Debug Control */
#define HWDC_R (1<<4) /* Reset & Hardware Failure */
#define HWDC_I (1<<3) /* Interrupts */
#define HWDC_S (1<<2) /* System Calls */
#define HWDC_E (1<<1) /* Program Errors */
#define HWDC_D (1<<0) /* Debug Exceptions */
enum esirisc_cache {
ESIRISC_CACHE_VON_NEUMANN,
ESIRISC_CACHE_HARVARD,
};
struct esirisc_common {
struct target *target;
struct esirisc_jtag jtag_info;
enum esirisc_cache cache_arch;
char *gdb_arch;
struct reg_cache *reg_cache;
struct reg *epc;
struct reg *ecas;
struct reg *eid;
struct reg *ed;
uint32_t etc_save;
uint32_t hwdc_save;
int num_bits;
int num_regs;
bool has_icache;
bool has_dcache;
int num_breakpoints;
int num_watchpoints;
struct breakpoint *breakpoints_p[MAX_BREAKPOINTS];
struct watchpoint *watchpoints_p[MAX_WATCHPOINTS];
};
union esirisc_memory {
uint32_t word;
uint16_t hword;
uint8_t byte;
};
struct esirisc_reg {
struct esirisc_common *esirisc;
uint8_t bank;
uint8_t csr;
int (*read)(struct reg *reg);
int (*write)(struct reg *reg);
};
static inline struct esirisc_common *target_to_esirisc(struct target *target)
{
return (struct esirisc_common *)target->arch_info;
}
static inline char *esirisc_cache_arch(struct esirisc_common *esirisc)
{
return esirisc->cache_arch == ESIRISC_CACHE_HARVARD ? "harvard" : "von_neumann";
}
static inline bool esirisc_has_cache(struct esirisc_common *esirisc)
{
return esirisc->has_icache || esirisc->has_dcache;
}
#endif /* OPENOCD_TARGET_ESIRISC_H */

514
src/target/esirisc_jtag.c Normal file
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@@ -0,0 +1,514 @@
/***************************************************************************
* Copyright (C) 2018 by Square, Inc. *
* Steven Stallion <stallion@squareup.com> *
* James Zhao <hjz@squareup.com> *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include <helper/binarybuffer.h>
#include <helper/log.h>
#include <helper/types.h>
#include <jtag/jtag.h>
#include <jtag/commands.h>
#include <jtag/interface.h>
#include "esirisc_jtag.h"
static void esirisc_jtag_set_instr(struct esirisc_jtag *jtag_info, uint32_t new_instr)
{
struct jtag_tap *tap = jtag_info->tap;
if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr) {
struct scan_field field;
uint8_t t[4];
field.num_bits = tap->ir_length;
field.out_value = t;
buf_set_u32(t, 0, field.num_bits, new_instr);
field.in_value = NULL;
jtag_add_ir_scan(tap, &field, TAP_IDLE);
}
}
/*
* The data register is latched every 8 bits while in the Shift-DR state
* (Update-DR is not supported). This necessitates prepending padding
* bits to ensure data is aligned when multiple TAPs are present.
*/
static int esirisc_jtag_get_padding(void)
{
int padding = 0;
int bypass_devices = 0;
for (struct jtag_tap *tap = jtag_tap_next_enabled(NULL); tap != NULL;
tap = jtag_tap_next_enabled(tap))
if (tap->bypass)
bypass_devices++;
int num_bits = bypass_devices % 8;
if (num_bits > 0)
padding = 8 - num_bits;
return padding;
}
static int esirisc_jtag_count_bits(int num_fields, struct scan_field *fields)
{
int bit_count = 0;
for (int i = 0; i < num_fields; ++i)
bit_count += fields[i].num_bits;
return bit_count;
}
/*
* Data received from the target will be byte-stuffed if it contains
* either the pad byte (0xAA) or stuffing marker (0x55). Buffers should
* be sized twice the expected length to account for stuffing overhead.
*/
static void esirisc_jtag_unstuff(uint8_t *data, size_t len)
{
uint8_t *r, *w;
uint8_t *end;
r = w = data;
end = data + len;
while (r < end) {
if (*r == STUFF_MARKER) {
r++; /* skip stuffing marker */
assert(r < end);
*w++ = *r++ ^ STUFF_MARKER;
} else
*w++ = *r++;
}
}
/*
* The eSi-Debug protocol defines a byte-oriented command/response
* channel that operates over serial or JTAG. While not strictly
* required, separate DR scans are used for sending and receiving data.
* This allows the TAP to recover gracefully if the byte stream is
* corrupted at the expense of sending additional padding bits.
*/
static int esirisc_jtag_send(struct esirisc_jtag *jtag_info, uint8_t command,
int num_out_fields, struct scan_field *out_fields)
{
int num_fields = 2 + num_out_fields;
struct scan_field *fields = cmd_queue_alloc(num_fields * sizeof(struct scan_field));
esirisc_jtag_set_instr(jtag_info, INSTR_DEBUG);
fields[0].num_bits = esirisc_jtag_get_padding();
fields[0].out_value = NULL;
fields[0].in_value = NULL;
fields[1].num_bits = 8;
fields[1].out_value = &command;
fields[1].in_value = NULL;
/* append command data */
for (int i = 0; i < num_out_fields; ++i)
jtag_scan_field_clone(&fields[2+i], &out_fields[i]);
jtag_add_dr_scan(jtag_info->tap, num_fields, fields, TAP_IDLE);
return jtag_execute_queue();
}
static int esirisc_jtag_recv(struct esirisc_jtag *jtag_info,
int num_in_fields, struct scan_field *in_fields)
{
int num_in_bits = esirisc_jtag_count_bits(num_in_fields, in_fields);
int num_in_bytes = DIV_ROUND_UP(num_in_bits, 8);
struct scan_field fields[3];
uint8_t r[num_in_bytes * 2];
esirisc_jtag_set_instr(jtag_info, INSTR_DEBUG);
fields[0].num_bits = esirisc_jtag_get_padding() + 1;
fields[0].out_value = NULL;
fields[0].in_value = NULL;
fields[1].num_bits = 8;
fields[1].out_value = NULL;
fields[1].in_value = &jtag_info->status;
fields[2].num_bits = num_in_bits * 2;
fields[2].out_value = NULL;
fields[2].in_value = r;
jtag_add_dr_scan(jtag_info->tap, ARRAY_SIZE(fields), fields, TAP_IDLE);
int retval = jtag_execute_queue();
if (retval != ERROR_OK)
return retval;
/* unstuff response data and write back to caller */
if (num_in_fields > 0) {
esirisc_jtag_unstuff(r, ARRAY_SIZE(r));
int bit_count = 0;
for (int i = 0; i < num_in_fields; ++i) {
buf_set_buf(r, bit_count, in_fields[i].in_value, 0, in_fields[i].num_bits);
bit_count += in_fields[i].num_bits;
}
}
return ERROR_OK;
}
static int esirisc_jtag_check_status(struct esirisc_jtag *jtag_info)
{
uint8_t eid = esirisc_jtag_get_eid(jtag_info);
if (eid != EID_NONE) {
LOG_ERROR("esirisc_jtag: bad status: 0x%02" PRIx32 " (DA: %" PRId32 ", "
"S: %" PRId32 ", EID: 0x%02" PRIx32 ")",
jtag_info->status, esirisc_jtag_is_debug_active(jtag_info),
esirisc_jtag_is_stopped(jtag_info), eid);
return ERROR_FAIL;
}
return ERROR_OK;
}
static int esirisc_jtag_send_and_recv(struct esirisc_jtag *jtag_info, uint8_t command,
int num_out_fields, struct scan_field *out_fields,
int num_in_fields, struct scan_field *in_fields)
{
int retval;
jtag_info->status = 0; /* clear status */
retval = esirisc_jtag_send(jtag_info, command, num_out_fields, out_fields);
if (retval != ERROR_OK) {
LOG_ERROR("esirisc_jtag: send failed (command: 0x%02" PRIx32 ")", command);
return ERROR_FAIL;
}
retval = esirisc_jtag_recv(jtag_info, num_in_fields, in_fields);
if (retval != ERROR_OK) {
LOG_ERROR("esirisc_jtag: recv failed (command: 0x%02" PRIx32 ")", command);
return ERROR_FAIL;
}
return esirisc_jtag_check_status(jtag_info);
}
/*
* Status is automatically updated after each command completes;
* these functions make each field available to the caller.
*/
bool esirisc_jtag_is_debug_active(struct esirisc_jtag *jtag_info)
{
return !!(jtag_info->status & 1<<7); /* DA */
}
bool esirisc_jtag_is_stopped(struct esirisc_jtag *jtag_info)
{
return !!(jtag_info->status & 1<<6); /* S */
}
uint8_t esirisc_jtag_get_eid(struct esirisc_jtag *jtag_info)
{
return jtag_info->status & 0x3f; /* EID */
}
/*
* Most commands manipulate target data (eg. memory and registers); each
* command returns a status byte that indicates success. Commands must
* transmit multibyte values in big-endian order, however response
* values are in little-endian order. Target endianness does not have an
* effect on this ordering.
*/
int esirisc_jtag_read_byte(struct esirisc_jtag *jtag_info, uint32_t address, uint8_t *data)
{
struct scan_field out_fields[1];
uint8_t a[4];
out_fields[0].num_bits = 32;
out_fields[0].out_value = a;
h_u32_to_be(a, address);
out_fields[0].in_value = NULL;
struct scan_field in_fields[1];
uint8_t d[1];
in_fields[0].num_bits = 8;
in_fields[0].out_value = NULL;
in_fields[0].in_value = d;
int retval = esirisc_jtag_send_and_recv(jtag_info, DEBUG_READ_BYTE,
ARRAY_SIZE(out_fields), out_fields, ARRAY_SIZE(in_fields), in_fields);
if (retval != ERROR_OK)
return retval;
*data = *d;
return ERROR_OK;
}
int esirisc_jtag_read_hword(struct esirisc_jtag *jtag_info, uint32_t address, uint16_t *data)
{
struct scan_field out_fields[1];
uint8_t a[4];
out_fields[0].num_bits = 32;
out_fields[0].out_value = a;
h_u32_to_be(a, address);
out_fields[0].in_value = NULL;
struct scan_field in_fields[1];
uint8_t d[2];
in_fields[0].num_bits = 16;
in_fields[0].out_value = NULL;
in_fields[0].in_value = d;
int retval = esirisc_jtag_send_and_recv(jtag_info, DEBUG_READ_HWORD,
ARRAY_SIZE(out_fields), out_fields, ARRAY_SIZE(in_fields), in_fields);
if (retval != ERROR_OK)
return retval;
*data = le_to_h_u16(d);
return ERROR_OK;
}
int esirisc_jtag_read_word(struct esirisc_jtag *jtag_info, uint32_t address, uint32_t *data)
{
struct scan_field out_fields[1];
uint8_t a[4];
out_fields[0].num_bits = 32;
out_fields[0].out_value = a;
h_u32_to_be(a, address);
out_fields[0].in_value = NULL;
struct scan_field in_fields[1];
uint8_t d[4];
in_fields[0].num_bits = 32;
in_fields[0].out_value = NULL;
in_fields[0].in_value = d;
int retval = esirisc_jtag_send_and_recv(jtag_info, DEBUG_READ_WORD,
ARRAY_SIZE(out_fields), out_fields, ARRAY_SIZE(in_fields), in_fields);
if (retval != ERROR_OK)
return retval;
*data = le_to_h_u32(d);
return ERROR_OK;
}
int esirisc_jtag_write_byte(struct esirisc_jtag *jtag_info, uint32_t address, uint8_t data)
{
struct scan_field out_fields[2];
uint8_t a[4];
out_fields[0].num_bits = 32;
out_fields[0].out_value = a;
h_u32_to_be(a, address);
out_fields[0].in_value = NULL;
out_fields[1].num_bits = 8;
out_fields[1].out_value = &data;
out_fields[1].in_value = NULL;
return esirisc_jtag_send_and_recv(jtag_info, DEBUG_WRITE_BYTE,
ARRAY_SIZE(out_fields), out_fields, 0, NULL);
}
int esirisc_jtag_write_hword(struct esirisc_jtag *jtag_info, uint32_t address, uint16_t data)
{
struct scan_field out_fields[2];
uint8_t a[4], d[2];
out_fields[0].num_bits = 32;
out_fields[0].out_value = a;
h_u32_to_be(a, address);
out_fields[0].in_value = NULL;
out_fields[1].num_bits = 16;
out_fields[1].out_value = d;
h_u16_to_be(d, data);
out_fields[1].in_value = NULL;
return esirisc_jtag_send_and_recv(jtag_info, DEBUG_WRITE_HWORD,
ARRAY_SIZE(out_fields), out_fields, 0, NULL);
}
int esirisc_jtag_write_word(struct esirisc_jtag *jtag_info, uint32_t address, uint32_t data)
{
struct scan_field out_fields[2];
uint8_t a[4], d[4];
out_fields[0].num_bits = 32;
out_fields[0].out_value = a;
h_u32_to_be(a, address);
out_fields[0].in_value = NULL;
out_fields[1].num_bits = 32;
out_fields[1].out_value = d;
h_u32_to_be(d, data);
out_fields[1].in_value = NULL;
return esirisc_jtag_send_and_recv(jtag_info, DEBUG_WRITE_WORD,
ARRAY_SIZE(out_fields), out_fields, 0, NULL);
}
int esirisc_jtag_read_reg(struct esirisc_jtag *jtag_info, uint8_t reg, uint32_t *data)
{
struct scan_field out_fields[1];
out_fields[0].num_bits = 8;
out_fields[0].out_value = &reg;
out_fields[0].in_value = NULL;
struct scan_field in_fields[1];
uint8_t d[4];
in_fields[0].num_bits = 32;
in_fields[0].out_value = NULL;
in_fields[0].in_value = d;
int retval = esirisc_jtag_send_and_recv(jtag_info, DEBUG_READ_REG,
ARRAY_SIZE(out_fields), out_fields, ARRAY_SIZE(in_fields), in_fields);
if (retval != ERROR_OK)
return retval;
*data = le_to_h_u32(d);
return ERROR_OK;
}
int esirisc_jtag_write_reg(struct esirisc_jtag *jtag_info, uint8_t reg, uint32_t data)
{
struct scan_field out_fields[2];
uint8_t d[4];
out_fields[0].num_bits = 8;
out_fields[0].out_value = &reg;
out_fields[0].in_value = NULL;
out_fields[1].num_bits = 32;
out_fields[1].out_value = d;
h_u32_to_be(d, data);
out_fields[1].in_value = NULL;
return esirisc_jtag_send_and_recv(jtag_info, DEBUG_WRITE_REG,
ARRAY_SIZE(out_fields), out_fields, 0, NULL);
}
int esirisc_jtag_read_csr(struct esirisc_jtag *jtag_info, uint8_t bank, uint8_t csr, uint32_t *data)
{
struct scan_field out_fields[1];
uint8_t c[2];
out_fields[0].num_bits = 16;
out_fields[0].out_value = c;
h_u16_to_be(c, (csr << 5) | bank);
out_fields[0].in_value = NULL;
struct scan_field in_fields[1];
uint8_t d[4];
in_fields[0].num_bits = 32;
in_fields[0].out_value = NULL;
in_fields[0].in_value = d;
int retval = esirisc_jtag_send_and_recv(jtag_info, DEBUG_READ_CSR,
ARRAY_SIZE(out_fields), out_fields, ARRAY_SIZE(in_fields), in_fields);
if (retval != ERROR_OK)
return retval;
*data = le_to_h_u32(d);
return ERROR_OK;
}
int esirisc_jtag_write_csr(struct esirisc_jtag *jtag_info, uint8_t bank, uint8_t csr, uint32_t data)
{
struct scan_field out_fields[2];
uint8_t c[2], d[4];
out_fields[0].num_bits = 16;
out_fields[0].out_value = c;
h_u16_to_be(c, (csr << 5) | bank);
out_fields[0].in_value = NULL;
out_fields[1].num_bits = 32;
out_fields[1].out_value = d;
h_u32_to_be(d, data);
out_fields[1].in_value = NULL;
return esirisc_jtag_send_and_recv(jtag_info, DEBUG_WRITE_CSR,
ARRAY_SIZE(out_fields), out_fields, 0, NULL);
}
/*
* Control commands affect CPU operation; these commands send no data
* and return a status byte.
*/
static inline int esirisc_jtag_send_ctrl(struct esirisc_jtag *jtag_info, uint8_t command)
{
return esirisc_jtag_send_and_recv(jtag_info, command, 0, NULL, 0, NULL);
}
int esirisc_jtag_enable_debug(struct esirisc_jtag *jtag_info)
{
return esirisc_jtag_send_ctrl(jtag_info, DEBUG_ENABLE_DEBUG);
}
int esirisc_jtag_disable_debug(struct esirisc_jtag *jtag_info)
{
return esirisc_jtag_send_ctrl(jtag_info, DEBUG_DISABLE_DEBUG);
}
int esirisc_jtag_assert_reset(struct esirisc_jtag *jtag_info)
{
return esirisc_jtag_send_ctrl(jtag_info, DEBUG_ASSERT_RESET);
}
int esirisc_jtag_deassert_reset(struct esirisc_jtag *jtag_info)
{
return esirisc_jtag_send_ctrl(jtag_info, DEBUG_DEASSERT_RESET);
}
int esirisc_jtag_break(struct esirisc_jtag *jtag_info)
{
return esirisc_jtag_send_ctrl(jtag_info, DEBUG_BREAK);
}
int esirisc_jtag_continue(struct esirisc_jtag *jtag_info)
{
return esirisc_jtag_send_ctrl(jtag_info, DEBUG_CONTINUE);
}
int esirisc_jtag_flush_caches(struct esirisc_jtag *jtag_info)
{
return esirisc_jtag_send_ctrl(jtag_info, DEBUG_FLUSH_CACHES);
}

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src/target/esirisc_jtag.h Normal file
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/***************************************************************************
* Copyright (C) 2018 by Square, Inc. *
* Steven Stallion <stallion@squareup.com> *
* James Zhao <hjz@squareup.com> *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#ifndef OPENOCD_TARGET_ESIRISC_JTAG_H
#define OPENOCD_TARGET_ESIRISC_JTAG_H
#include <jtag/jtag.h>
/* TAP Instructions */
#define INSTR_IDCODE 0x8
#define INSTR_DEBUG 0x9
#define INSTR_BYPASS 0xf
#define INSTR_LENGTH 4
/* eSi-Debug Commands */
#define DEBUG_NOP 0x00
#define DEBUG_READ_BYTE 0x10
#define DEBUG_READ_HWORD 0x20
#define DEBUG_READ_WORD 0x30
#define DEBUG_WRITE_BYTE 0x60
#define DEBUG_WRITE_HWORD 0x70
#define DEBUG_WRITE_WORD 0x80
#define DEBUG_READ_REG 0xb0
#define DEBUG_WRITE_REG 0xc0
#define DEBUG_READ_CSR 0xd0
#define DEBUG_WRITE_CSR 0xe0
#define DEBUG_ENABLE_DEBUG 0xf0
#define DEBUG_DISABLE_DEBUG 0xf2
#define DEBUG_ASSERT_RESET 0xf4
#define DEBUG_DEASSERT_RESET 0xf6
#define DEBUG_BREAK 0xf8
#define DEBUG_CONTINUE 0xfa
#define DEBUG_FLUSH_CACHES 0xfc
/* Exception IDs */
#define EID_OVERFLOW 0x3d
#define EID_CANT_DEBUG 0x3e
#define EID_NONE 0x3f
/* Byte Stuffing */
#define STUFF_MARKER 0x55
#define PAD_BYTE 0xaa
struct esirisc_jtag {
struct jtag_tap *tap;
uint8_t status;
};
bool esirisc_jtag_is_debug_active(struct esirisc_jtag *jtag_info);
bool esirisc_jtag_is_stopped(struct esirisc_jtag *jtag_info);
uint8_t esirisc_jtag_get_eid(struct esirisc_jtag *jtag_info);
int esirisc_jtag_read_byte(struct esirisc_jtag *jtag_info,
uint32_t address, uint8_t *data);
int esirisc_jtag_read_hword(struct esirisc_jtag *jtag_info,
uint32_t address, uint16_t *data);
int esirisc_jtag_read_word(struct esirisc_jtag *jtag_info,
uint32_t address, uint32_t *data);
int esirisc_jtag_write_byte(struct esirisc_jtag *jtag_info,
uint32_t address, uint8_t data);
int esirisc_jtag_write_hword(struct esirisc_jtag *jtag_info,
uint32_t address, uint16_t data);
int esirisc_jtag_write_word(struct esirisc_jtag *jtag_info,
uint32_t address, uint32_t data);
int esirisc_jtag_read_reg(struct esirisc_jtag *jtag_info,
uint8_t reg, uint32_t *data);
int esirisc_jtag_write_reg(struct esirisc_jtag *jtag_info,
uint8_t reg, uint32_t data);
int esirisc_jtag_read_csr(struct esirisc_jtag *jtag_info,
uint8_t bank, uint8_t csr, uint32_t *data);
int esirisc_jtag_write_csr(struct esirisc_jtag *jtag_info,
uint8_t bank, uint8_t csr, uint32_t data);
int esirisc_jtag_enable_debug(struct esirisc_jtag *jtag_info);
int esirisc_jtag_disable_debug(struct esirisc_jtag *jtag_info);
int esirisc_jtag_assert_reset(struct esirisc_jtag *jtag_info);
int esirisc_jtag_deassert_reset(struct esirisc_jtag *jtag_info);
int esirisc_jtag_break(struct esirisc_jtag *jtag_info);
int esirisc_jtag_continue(struct esirisc_jtag *jtag_info);
int esirisc_jtag_flush_caches(struct esirisc_jtag *jtag_info);
#endif /* OPENOCD_TARGET_ESIRISC_JTAG_H */

184
src/target/esirisc_regs.h Normal file
View File

@@ -0,0 +1,184 @@
/***************************************************************************
* Copyright (C) 2018 by Square, Inc. *
* Steven Stallion <stallion@squareup.com> *
* James Zhao <hjz@squareup.com> *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#ifndef OPENOCD_TARGET_ESIRISC_REGS_H
#define OPENOCD_TARGET_ESIRISC_REGS_H
enum esirisc_reg_num {
ESIRISC_SP,
ESIRISC_RA,
ESIRISC_R2,
ESIRISC_R3,
ESIRISC_R4,
ESIRISC_R5,
ESIRISC_R6,
ESIRISC_R7,
ESIRISC_R8,
ESIRISC_R9,
ESIRISC_R10,
ESIRISC_R11,
ESIRISC_R12,
ESIRISC_R13,
ESIRISC_R14,
ESIRISC_R15,
ESIRISC_R16,
ESIRISC_R17,
ESIRISC_R18,
ESIRISC_R19,
ESIRISC_R20,
ESIRISC_R21,
ESIRISC_R22,
ESIRISC_R23,
ESIRISC_R24,
ESIRISC_R25,
ESIRISC_R26,
ESIRISC_R27,
ESIRISC_R28,
ESIRISC_R29,
ESIRISC_R30,
ESIRISC_R31,
ESIRISC_V0,
ESIRISC_V1,
ESIRISC_V2,
ESIRISC_V3,
ESIRISC_V4,
ESIRISC_V5,
ESIRISC_V6,
ESIRISC_V7,
ESIRISC_V8,
ESIRISC_V9,
ESIRISC_V10,
ESIRISC_V11,
ESIRISC_V12,
ESIRISC_V13,
ESIRISC_V14,
ESIRISC_V15,
ESIRISC_V16,
ESIRISC_V17,
ESIRISC_V18,
ESIRISC_V19,
ESIRISC_V20,
ESIRISC_V21,
ESIRISC_V22,
ESIRISC_V23,
ESIRISC_V24,
ESIRISC_V25,
ESIRISC_V26,
ESIRISC_V27,
ESIRISC_V28,
ESIRISC_V29,
ESIRISC_V30,
ESIRISC_V31,
ESIRISC_A0,
ESIRISC_A1,
ESIRISC_A2,
ESIRISC_A3,
ESIRISC_A4,
ESIRISC_A5,
ESIRISC_A6,
ESIRISC_A7,
ESIRISC_PC,
ESIRISC_CAS,
ESIRISC_TC,
ESIRISC_ETA,
ESIRISC_ETC,
ESIRISC_EPC,
ESIRISC_ECAS,
ESIRISC_EID,
ESIRISC_ED,
ESIRISC_IP,
ESIRISC_IM,
ESIRISC_IS,
ESIRISC_IT,
ESIRISC_NUM_REGS,
};
/* CSR Banks */
#define CSR_THREAD 0x00
#define CSR_INTERRUPT 0x01
#define CSR_DEBUG 0x04
#define CSR_CONFIG 0x05
#define CSR_TRACE 0x09
/* Thread CSRs */
#define CSR_THREAD_TC 0x00 /* Thread Control */
#define CSR_THREAD_PC 0x01 /* Program Counter */
#define CSR_THREAD_CAS 0x02 /* Comparison & Arithmetic Status */
#define CSR_THREAD_AC 0x03 /* Arithmetic Control */
#define CSR_THREAD_LF 0x04 /* Locked Flag */
#define CSR_THREAD_LA 0x05 /* Locked Address */
#define CSR_THREAD_ETA 0x07 /* Exception Table Address */
#define CSR_THREAD_ETC 0x08 /* Exception TC */
#define CSR_THREAD_EPC 0x09 /* Exception PC */
#define CSR_THREAD_ECAS 0x0a /* Exception CAS */
#define CSR_THREAD_EID 0x0b /* Exception ID */
#define CSR_THREAD_ED 0x0c /* Exception Data */
/* Interrupt CSRs */
#define CSR_INTERRUPT_IP 0x00 /* Interrupt Pending */
#define CSR_INTERRUPT_IA 0x01 /* Interrupt Acknowledge */
#define CSR_INTERRUPT_IM 0x02 /* Interrupt Mask */
#define CSR_INTERRUPT_IS 0x03 /* Interrupt Sense */
#define CSR_INTERRUPT_IT 0x04 /* Interrupt Trigger */
/* Debug CSRs */
#define CSR_DEBUG_DC 0x00 /* Debug Control */
#define CSR_DEBUG_IBC 0x01 /* Instruction Breakpoint Control */
#define CSR_DEBUG_DBC 0x02 /* Data Breakpoint Control */
#define CSR_DEBUG_HWDC 0x03 /* Hardware Debug Control */
#define CSR_DEBUG_DBS 0x04 /* Data Breakpoint Size */
#define CSR_DEBUG_DBR 0x05 /* Data Breakpoint Range */
#define CSR_DEBUG_IBAn 0x08 /* Instruction Breakpoint Address [0..7] */
#define CSR_DEBUG_DBAn 0x10 /* Data Breakpoint Address [0..7] */
/* Configuration CSRs */
#define CSR_CONFIG_ARCH0 0x00 /* Architectural Configuration 0 */
#define CSR_CONFIG_ARCH1 0x01 /* Architectural Configuration 1 */
#define CSR_CONFIG_ARCH2 0x02 /* Architectural Configuration 2 */
#define CSR_CONFIG_ARCH3 0x03 /* Architectural Configuration 3 */
#define CSR_CONFIG_MEM 0x04 /* Memory Configuration */
#define CSR_CONFIG_IC 0x05 /* Instruction Cache Configuration */
#define CSR_CONFIG_DC 0x06 /* Data Cache Configuration */
#define CSR_CONFIG_INT 0x07 /* Interrupt Configuration */
#define CSR_CONFIG_ISAn 0x08 /* Instruction Set Configuration [0..6] */
#define CSR_CONFIG_DBG 0x0f /* Debug Configuration */
#define CSR_CONFIG_MID 0x10 /* Manufacturer ID */
#define CSR_CONFIG_REV 0x11 /* Revision Number */
#define CSR_CONFIG_MPID 0x12 /* Mulitprocessor ID */
#define CSR_CONFIG_FREQn 0x13 /* Frequency [0..2] */
#define CSR_CONFIG_TRACE 0x16 /* Trace Configuration */
/* Trace CSRs */
#define CSR_TRACE_CONTROL 0x00
#define CSR_TRACE_STATUS 0x01
#define CSR_TRACE_BUFFER_START 0x02
#define CSR_TRACE_BUFFER_END 0x03
#define CSR_TRACE_BUFFER_CUR 0x04
#define CSR_TRACE_TRIGGER 0x05
#define CSR_TRACE_START_DATA 0x06
#define CSR_TRACE_START_MASK 0x07
#define CSR_TRACE_STOP_DATA 0x08
#define CSR_TRACE_STOP_MASK 0x09
#define CSR_TRACE_DELAY 0x0a
#endif /* OPENOCD_TARGET_ESIRISC_REGS_H */

4
src/target/target.c
View File

@@ -109,6 +109,7 @@ extern struct target_type quark_d20xx_target;
extern struct target_type stm8_target;
extern struct target_type riscv_target;
extern struct target_type mem_ap_target;
extern struct target_type esirisc_target;
static struct target_type *target_types[] = {
&arm7tdmi_target,
@@ -142,10 +143,11 @@ static struct target_type *target_types[] = {
&quark_d20xx_target,
&stm8_target,
&riscv_target,
&mem_ap_target,
&esirisc_target,
#if BUILD_TARGET64
&aarch64_target,
#endif
&mem_ap_target,
NULL,
};

7
src/target/target.h
View File

@@ -225,6 +225,13 @@ struct gdb_fileio_info {
uint64_t param_4;
};
/** Returns a description of the endianness for the specified target. */
static inline const char *target_endianness(struct target *target)
{
return (target->endianness == TARGET_ENDIAN_UNKNOWN) ? "unknown" :
(target->endianness == TARGET_BIG_ENDIAN) ? "big endian" : "little endian";
}
/** Returns the instance-specific name of the specified target. */
static inline const char *target_name(struct target *target)
{