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esirisc: support eSi-RISC targets

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eSi-RISC is a highly configurable microprocessor architecture for
embedded systems provided by EnSilica. This patch adds support for
32-bit targets and also includes an internal flash driver and
uC/OS-III RTOS support. This is a non-traditional target and required
a number of additional changes to support non-linear register numbers
and the 'p' packet in RTOS support for proper integration into
EnSilica's GDB port.

Change-Id: I59d5c40b3bb2ace1b1a01b2538bfab211adf113f
Signed-off-by: Steven Stallion <stallion@squareup.com>
Reviewed-on: http://openocd.zylin.com/4660
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
This commit is contained in:
Steven Stallion
2018-08-28 17:18:01 -07:00
committed by Matthias Welwarsky
parent e72b2601e7
commit 4ab75a3634
17 changed files with 3496 additions and 9 deletions
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7
src/target/target.h
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@@ -225,6 +225,13 @@ struct gdb_fileio_info {
uint64_t param_4;
};
/** Returns a description of the endianness for the specified target. */
static inline const char *target_endianness(struct target *target)
{
return (target->endianness == TARGET_ENDIAN_UNKNOWN) ? "unknown" :
(target->endianness == TARGET_BIG_ENDIAN) ? "big endian" : "little endian";
}
/** Returns the instance-specific name of the specified target. */
static inline const char *target_name(struct target *target)
{