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adi_v5: Rename AP_REG_* to MEM_AP_REG_* and add LA support

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This is a TODO in the src/target/arm_adi_v5.h for MEM-AP registers.

Some new registers are introduced in ADIv5.2 specification.
  MEM_AP_REG_MGT    (0x20) // Memory Barrier Transfer register
  MEM_AP_REG_TAR64  (0x08) // Bits[63:32] of Transfer Address
  MEM_AP_REG_BASE64 (0xF0) // Bits[63:32] of Debug Base Address

Refer to
  7.5 MEM-AP register summary in
  IHI0031C: ARM Debug Interface Architecture Specification ADIv5.0 to ADIv5.2

Change-Id: I3bc4296a04c35f5c64f851e5865d3099922613fa
Signed-off-by: Alamy Liu <alamy.liu@gmail.com>
Reviewed-on: http://openocd.zylin.com/2904
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This commit is contained in:
Alamy Liu
2015-08-06 14:05:24 -07:00
committed by Andreas Fritiofson
parent f1dac60894
commit 4dc012865f
3 changed files with 30 additions and 29 deletions
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25
src/target/arm_adi_v5.h
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@@ -90,19 +90,20 @@
#define CSYSPWRUPACK (1UL << 31)
/* MEM-AP register addresses */
/* TODO: rename as MEM_AP_REG_* */
#define AP_REG_CSW 0x00
#define AP_REG_TAR 0x04
#define AP_REG_DRW 0x0C
#define AP_REG_BD0 0x10
#define AP_REG_BD1 0x14
#define AP_REG_BD2 0x18
#define AP_REG_BD3 0x1C
#define AP_REG_CFG 0xF4 /* big endian? */
#define AP_REG_BASE 0xF8
#define MEM_AP_REG_CSW 0x00
#define MEM_AP_REG_TAR 0x04
#define MEM_AP_REG_TAR64 0x08 /* RW: Large Physical Address Extension */
#define MEM_AP_REG_DRW 0x0C /* RW: Data Read/Write register */
#define MEM_AP_REG_BD0 0x10 /* RW: Banked Data register 0-3 */
#define MEM_AP_REG_BD1 0x14
#define MEM_AP_REG_BD2 0x18
#define MEM_AP_REG_BD3 0x1C
#define MEM_AP_REG_MBT 0x20 /* --: Memory Barrier Transfer register */
#define MEM_AP_REG_BASE64 0xF0 /* RO: Debug Base Address (LA) register */
#define MEM_AP_REG_CFG 0xF4 /* RO: Configuration register */
#define MEM_AP_REG_BASE 0xF8 /* RO: Debug Base Address register */
/* Generic AP register address */
#define AP_REG_IDR 0xFC
#define AP_REG_IDR 0xFC /* RO: Identification Register */
/* Fields of the MEM-AP's CSW register */
#define CSW_8BIT 0