target/armv8: Handle instruction cache invalidate

Some armv8 target have separate i-cache and d-cache.
The actual code only handles the flush of the d-cache.

Change-Id: I61a223b43c71646bbbed8fa63825360c67700988
Signed-off-by: Adrien Grassein <agrassein@nanoxplore.com>
Signed-off-by: Adrien Charruel <acharruel@nanoxplore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8655
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins

src/target/armv8_opcodes.h

@@ -72,6 +72,8 @@
 #define SYSTEM_DCCISW			0x43F2
 #define SYSTEM_DCCSW			0x43D2
 #define SYSTEM_ICIVAU			0x5BA9
+/* Attention, SYSTEM_ICIALLU requires rt=0x1f */
+#define SYSTEM_ICIALLU			0x03A8
 #define SYSTEM_DCCVAU			0x5BD9
 #define SYSTEM_DCCIVAC			0x5BF1
 
@@ -207,6 +209,7 @@ enum armv8_opcode {
 	ARMV8_OPC_LDRH_IP,
 	ARMV8_OPC_LDRW_IP,
 	ARMV8_OPC_LDRD_IP,
+	ARMV8_OPC_ICIALLU,
 	ARMV8_OPC_NUM,
 };