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aarch64: cache identification for aarch32 state

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Use proper T32 opcodes for cache identification when the PE is in
Aarch32 state

Change-Id: I9cd9169409889273a3fd61167f388e68d8dde86d
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
This commit is contained in:
Matthias Welwarsky
2016-10-20 13:20:26 +02:00
parent 946958cb72
commit 62c2eb4b28
3 changed files with 14 additions and 6 deletions
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2
src/target/armv8_opcodes.c
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@@ -24,6 +24,7 @@
#include "armv8_opcodes.h"
static const uint32_t a64_opcodes[ARMV8_OPC_NUM] = {
[READ_REG_CTR] = ARMV8_MRS(SYSTEM_CTR, 0),
[READ_REG_CLIDR] = ARMV8_MRS(SYSTEM_CLIDR, 0),
[READ_REG_CSSELR] = ARMV8_MRS(SYSTEM_CSSELR, 0),
[READ_REG_CCSIDR] = ARMV8_MRS(SYSTEM_CCSIDR, 0),
@@ -39,6 +40,7 @@ static const uint32_t a64_opcodes[ARMV8_OPC_NUM] = {
};
static const uint32_t t32_opcodes[ARMV8_OPC_NUM] = {
[READ_REG_CTR] = ARMV4_5_MRC(15, 0, 0, 0, 0, 1),
[READ_REG_CLIDR] = ARMV4_5_MRC(15, 1, 0, 0, 0, 1),
[READ_REG_CSSELR] = ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
[READ_REG_CCSIDR] = ARMV4_5_MRC(15, 1, 0, 0, 0, 0),