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aarch64: cache identification for aarch32 state

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Use proper T32 opcodes for cache identification when the PE is in
Aarch32 state

Change-Id: I9cd9169409889273a3fd61167f388e68d8dde86d
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
This commit is contained in:
Matthias Welwarsky
2016-10-20 13:20:26 +02:00
parent 946958cb72
commit 62c2eb4b28
3 changed files with 14 additions and 6 deletions
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src/target/armv8_opcodes.h
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@@ -160,6 +160,7 @@
#define ARMV8_SYS(System, Rt) (0xD5080000 | ((System) << 5) | Rt)
enum armv8_opcode {
READ_REG_CTR,
READ_REG_CLIDR,
READ_REG_CSSELR,
READ_REG_CCSIDR,