auracaster/sw_openocd
3
0
Fork 0
forked from auracaster/openocd
Code Pull Requests Activity

rename nand.h to flash//nand/core.h

Browse Source 
Rename nand.h as flash/nand/core.h, chase consumers.  The public APIs
need to be sorted out with imp.h, but this allows other changes to
begin improving the separation between policy and mechanism.

Moves #include <target/target.h> and #include "driver.h" into the
internal headers or source files, removing it from <flash/nand/core.h>.
This commit is contained in:
Zachary T Welch
2009-12-04 22:04:37 -08:00
parent da3bcb392e
commit 899c9975e7
20 changed files with 33 additions and 28 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/flash/nand/Makefile.am
View File

@@ -26,6 +26,7 @@ NAND_DRIVERS = \
noinst_HEADERS = \
arm_io.h \
core.h \
lpc3180.h \
driver.h \
mx3.h \

3
src/flash/nand/arm_io.c
View File

@@ -24,10 +24,13 @@
#include "config.h"
#endif
#include "core.h"
#include "arm_io.h"
#include <helper/binarybuffer.h>
#include <target/armv4_5.h>
#include <target/algorithm.h>
/**
* Copies code to a working area. This will allocate room for the code plus the
* additional amount requested if the working area pointer is null.

3
src/flash/nand/arm_io.h
View File

@@ -19,9 +19,6 @@
#ifndef __ARM_NANDIO_H
#define __ARM_NANDIO_H
#include <flash/nand.h>
#include <helper/binarybuffer.h>
/**
* Available operational states the arm_nand_data struct can be in.
*/

2
src/flash/nand/core.c
View File

@@ -24,8 +24,6 @@
#include "config.h"
#endif
#include <flash/nand.h>
#include <flash/common.h>
#include "imp.h"
/* configured NAND devices and NAND Flash command handler */

243
src/flash/nand/core.h Normal file
View File

@@ -0,0 +1,243 @@
/***************************************************************************
* Copyright (C) 2007 by Dominic Rath <Dominic.Rath@gmx.de> *
* Copyright (C) 2009 Zachary T Welch <zw@superlucidity.net> *
* *
* Partially based on linux/include/linux/mtd/nand.h *
* Copyright (C) 2000 David Woodhouse <dwmw2@mvhi.com> *
* Copyright (C) 2000 Steven J. Hill <sjhill@realitydiluted.com> *
* Copyright (C) 2000 Thomas Gleixner <tglx@linutronix.de> *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#ifndef FLASH_NAND_CORE_H
#define FLASH_NAND_CORE_H
#include <flash/common.h>
/**
* Representation of a single NAND block in a NAND device.
*/
struct nand_block
{
/** Offset to the block. */
uint32_t offset;
/** Size of the block. */
uint32_t size;
/** True if the block has been erased. */
int is_erased;
/** True if the block is bad. */
int is_bad;
};
struct nand_oobfree {
int offset;
int length;
};
struct nand_ecclayout {
int eccbytes;
int eccpos[64];
int oobavail;
struct nand_oobfree oobfree[2];
};
struct nand_device
{
char *name;
struct nand_flash_controller *controller;
void *controller_priv;
struct nand_manufacturer *manufacturer;
struct nand_info *device;
int bus_width;
int address_cycles;
int page_size;
int erase_size;
int use_raw;
int num_blocks;
struct nand_block *blocks;
struct nand_device *next;
};
/* NAND Flash Manufacturer ID Codes
*/
enum
{
NAND_MFR_TOSHIBA = 0x98,
NAND_MFR_SAMSUNG = 0xec,
NAND_MFR_FUJITSU = 0x04,
NAND_MFR_NATIONAL = 0x8f,
NAND_MFR_RENESAS = 0x07,
NAND_MFR_STMICRO = 0x20,
NAND_MFR_HYNIX = 0xad,
NAND_MFR_MICRON = 0x2c,
};
struct nand_manufacturer
{
int id;
char *name;
};
struct nand_info
{
char *name;
int id;
int page_size;
int chip_size;
int erase_size;
int options;
};
/* Option constants for bizarre disfunctionality and real features
*/
enum {
/* Chip can not auto increment pages */
NAND_NO_AUTOINCR = 0x00000001,
/* Buswitdh is 16 bit */
NAND_BUSWIDTH_16 = 0x00000002,
/* Device supports partial programming without padding */
NAND_NO_PADDING = 0x00000004,
/* Chip has cache program function */
NAND_CACHEPRG = 0x00000008,
/* Chip has copy back function */
NAND_COPYBACK = 0x00000010,
/* AND Chip which has 4 banks and a confusing page / block
* assignment. See Renesas datasheet for further information */
NAND_IS_AND = 0x00000020,
/* Chip has a array of 4 pages which can be read without
* additional ready /busy waits */
NAND_4PAGE_ARRAY = 0x00000040,
/* Chip requires that BBT is periodically rewritten to prevent
* bits from adjacent blocks from 'leaking' in altering data.
* This happens with the Renesas AG-AND chips, possibly others. */
BBT_AUTO_REFRESH = 0x00000080,
/* Chip does not require ready check on read. True
* for all large page devices, as they do not support
* autoincrement.*/
NAND_NO_READRDY = 0x00000100,
/* Options valid for Samsung large page devices */
NAND_SAMSUNG_LP_OPTIONS = (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK),
/* Options for new chips with large page size. The pagesize and the
* erasesize is determined from the extended id bytes
*/
LP_OPTIONS = (NAND_SAMSUNG_LP_OPTIONS | NAND_NO_READRDY | NAND_NO_AUTOINCR),
LP_OPTIONS16 = (LP_OPTIONS | NAND_BUSWIDTH_16),
};
enum
{
/* Standard NAND flash commands */
NAND_CMD_READ0 = 0x0,
NAND_CMD_READ1 = 0x1,
NAND_CMD_RNDOUT = 0x5,
NAND_CMD_PAGEPROG = 0x10,
NAND_CMD_READOOB = 0x50,
NAND_CMD_ERASE1 = 0x60,
NAND_CMD_STATUS = 0x70,
NAND_CMD_STATUS_MULTI = 0x71,
NAND_CMD_SEQIN = 0x80,
NAND_CMD_RNDIN = 0x85,
NAND_CMD_READID = 0x90,
NAND_CMD_ERASE2 = 0xd0,
NAND_CMD_RESET = 0xff,
/* Extended commands for large page devices */
NAND_CMD_READSTART = 0x30,
NAND_CMD_RNDOUTSTART = 0xE0,
NAND_CMD_CACHEDPROG = 0x15,
};
/* Status bits */
enum
{
NAND_STATUS_FAIL = 0x01,
NAND_STATUS_FAIL_N1 = 0x02,
NAND_STATUS_TRUE_READY = 0x20,
NAND_STATUS_READY = 0x40,
NAND_STATUS_WP = 0x80,
};
/* OOB (spare) data formats */
enum oob_formats
{
NAND_OOB_NONE = 0x0, /* no OOB data at all */
NAND_OOB_RAW = 0x1, /* raw OOB data (16 bytes for 512b page sizes, 64 bytes for 2048b page sizes) */
NAND_OOB_ONLY = 0x2, /* only OOB data */
NAND_OOB_SW_ECC = 0x10, /* when writing, use SW ECC (as opposed to no ECC) */
NAND_OOB_HW_ECC = 0x20, /* when writing, use HW ECC (as opposed to no ECC) */
NAND_OOB_SW_ECC_KW = 0x40, /* when writing, use Marvell's Kirkwood bootrom format */
NAND_OOB_JFFS2 = 0x100, /* when writing, use JFFS2 OOB layout */
NAND_OOB_YAFFS2 = 0x100,/* when writing, use YAFFS2 OOB layout */
};
/**
* Returns the flash bank specified by @a name, which matches the
* driver name and a suffix (option) specify the driver-specific
* bank number. The suffix consists of the '.' and the driver-specific
* bank number: when two davinci banks are defined, then 'davinci.1' refers
* to the second (e.g. DM355EVM).
*/
struct nand_device *get_nand_device_by_name(const char *name);
struct nand_device *get_nand_device_by_num(int num);
int nand_page_command(struct nand_device *nand, uint32_t page,
uint8_t cmd, bool oob_only);
int nand_read_page_raw(struct nand_device *nand, uint32_t page,
uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
int nand_write_page_raw(struct nand_device *nand, uint32_t page,
uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
int nand_read_status(struct nand_device *nand, uint8_t *status);
int nand_calculate_ecc(struct nand_device *nand,
const uint8_t *dat, uint8_t *ecc_code);
int nand_calculate_ecc_kw(struct nand_device *nand,
const uint8_t *dat, uint8_t *ecc_code);
int nand_register_commands(struct command_context *cmd_ctx);
int nand_init(struct command_context *cmd_ctx);
/// helper for parsing a nand device command argument string
COMMAND_HELPER(nand_command_get_device, unsigned name_index,
struct nand_device **nand);
#define ERROR_NAND_DEVICE_INVALID (-1100)
#define ERROR_NAND_OPERATION_FAILED (-1101)
#define ERROR_NAND_OPERATION_TIMEOUT (-1102)
#define ERROR_NAND_OPERATION_NOT_SUPPORTED (-1103)
#define ERROR_NAND_DEVICE_NOT_PROBED (-1104)
#define ERROR_NAND_ERROR_CORRECTION_FAILED (-1105)
#define ERROR_NAND_NO_BUFFER (-1106)
#endif // FLASH_NAND_CORE_H

3
src/flash/nand/davinci.c
View File

@@ -28,8 +28,9 @@
#include "config.h"
#endif
#include "imp.h"
#include "arm_io.h"
#include <target/target.h>
enum ecc {
HWECC1, /* all controllers support 1-bit ECC */

2
src/flash/nand/driver.c
View File

@@ -23,7 +23,7 @@
#ifdef HAVE_CONFIG_H
#include <config.h>
#endif
#include <flash/nand.h>
#include "core.h"
#include "driver.h"
/* NAND flash controller

2
src/flash/nand/ecc.c
View File

@@ -41,7 +41,7 @@
#include "config.h"
#endif
#include <flash/nand.h>
#include "core.h"
/*
* Pre-calculated 256-way 1 byte column parity

2
src/flash/nand/ecc_kw.c
View File

@@ -20,7 +20,7 @@
#include "config.h"
#endif
#include <flash/nand.h>
#include "core.h"
/*****************************************************************************
* Arithmetic in GF(2^10) ("F") modulo x^10 + x^3 + 1.

2
src/flash/nand/fileio.c
View File

@@ -24,7 +24,7 @@
#include "config.h"
#endif
#include <flash/nand.h>
#include "core.h"
#include "fileio.h"
static struct nand_ecclayout nand_oob_16 = {

3
src/flash/nand/imp.h
View File

@@ -19,6 +19,9 @@
#ifndef FLASH_NAND_IMP_H
#define FLASH_NAND_IMP_H
#include "core.h"
#include "driver.h"
int nand_write_page(struct nand_device *nand,
uint32_t page, uint8_t *data, uint32_t data_size,
uint8_t *oob, uint32_t oob_size);

4
src/flash/nand/lpc3180.c
View File

@@ -21,8 +21,10 @@
#include "config.h"
#endif
#include "imp.h"
#include "lpc3180.h"
#include <flash/nand.h>
#include <target/target.h>
static int lpc3180_reset(struct nand_device *nand);
static int lpc3180_controller_ready(struct nand_device *nand, int timeout);

2
src/flash/nand/mx3.c
View File

@@ -35,7 +35,9 @@ get_next_halfword_from_sram_buffer() not tested
#include "config.h"
#endif
#include "imp.h"
#include "mx3.h"
#include <target/target.h>
static const char target_not_halted_err_msg[] =
"target must be halted to use mx3 NAND flash controller";

1
src/flash/nand/mx3.h
View File

@@ -25,7 +25,6 @@
*
* Many thanks to Ben Dooks for writing s3c24xx driver.
*/
#include <flash/nand.h>
#define MX3_NF_BASE_ADDR 0xb8000000
#define MX3_NF_BUFSIZ (MX3_NF_BASE_ADDR + 0xe00)

3
src/flash/nand/nonce.c
View File

@@ -20,7 +20,8 @@
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include <flash/nand.h>
#include "imp.h"
#include "hello.h"

1
src/flash/nand/orion.c
View File

@@ -26,6 +26,7 @@
#include "config.h"
#endif
#include "imp.h"
#include "arm_io.h"
#include <target/armv4_5.h>

5
src/flash/nand/s3c24xx.h
View File

@@ -27,8 +27,9 @@
* Many thanks to Simtec Electronics for sponsoring this work.
*/
#include <flash/nand.h>
#include <flash/nand/s3c24xx_regs.h>
#include "imp.h"
#include "s3c24xx_regs.h"
#include <target/target.h>
struct s3c24xx_nand_controller
{

2
src/flash/nand/tcl.c
View File

@@ -24,7 +24,7 @@
#include "config.h"
#endif
#include <flash/nand.h>
#include "core.h"
#include "imp.h"
#include "fileio.h"