forked from auracaster/openocd
Comment and doxygen fixes
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This commit is contained in:
@@ -26,6 +26,11 @@
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#ifndef __ARM_OPCODES_H
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#define __ARM_OPCODES_H
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/**
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* @file
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* Macros used to generate various ARM or Thumb opcodes.
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*/
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/* ARM mode instructions */
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/* Store multiple increment after
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@@ -145,9 +150,13 @@
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/* Thumb mode instructions
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*
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* FIXME there must be some reason all these opcodes are 32-bits
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* not 16-bits ... this should get either an explanatory comment,
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* or be changed not to duplicate the opcode.
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* NOTE: these 16-bit opcodes fill both halves of a word with the same
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* value. The reason for this is that when we need to execute Thumb
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* opcodes on ARM7/ARM9 cores (to switch to ARM state on debug entry),
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* we must shift 32 bits to the bus using scan chain 1 ... if we write
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* both halves, we don't need to track which half matters. On ARMv6 and
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* ARMv7 we don't execute Thumb instructions in debug mode; the ITR
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* register does not accept Thumb (or Thumb2) opcodes.
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*/
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/* Store register (Thumb mode)
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