auracaster/sw_openocd
3
0
Fork 0
forked from auracaster/openocd
Code Pull Requests Activity

target: cortex-m: defer cache identification on Cortex-M85 under reset

Browse Source 
Like for Cortex-M7, also Cortex-M85 prevents detecting the cache
properties when the CPU is kept under reset.

Extend to Cortex-M85 the same deferred mechanism already in place
for Cortex-M7.

Change-Id: Id274bb6c0b46c568554eed9671ef690c34cf7cfa
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9397
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Marc Schink <dev@zapb.de>
This commit is contained in:
Antonio Borneo
2026-01-22 16:23:45 +01:00
parent 294538f0d4
commit 95bd9093b1
1 changed files with 14 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
src/target/armv7m_cache.c
View File

@@ -192,28 +192,37 @@ static int armv7m_identify_cache_internal(struct target *target)
}
/*
* On Cortex-M7 only, when the CPU is kept in reset, several registers of the
* System Control Space (SCS) are not accessible and return bus error.
* The list of accessible registers is:
* On Cortex-M7 and Cortex-M85, when the CPU is kept in reset, several
* registers of the System Control Space (SCS) are not accessible and
* return bus error.
* The list of accessible registers for Cortex-M7 is:
* - 0xE000ED00
* - 0xE000ED30
* - 0xE000EDF0 ... 0xE000EEFC
* - 0xE000EF40 ... 0xE000EF48
* - 0xE000EFD0 ... 0xE000EFFC
* The list of accessible registers for Cortex-M85 is:
* - 0xE000ED00
* - 0xE000ED30
* - 0xE000ED40 ... 0xE000ED80
* - 0xE000EDF0 ... 0xE000EEFC
* - 0xE000EF40 ... 0xE000EF4C
* - 0xE000EFB0 ... 0xE000EFFC
* This makes impossible detecting the cache during the reset.
* Use a deferred mechanism to detect the cache during polling or when the
* Cortex-M7 halts.
* CPU halts.
*/
int armv7m_identify_cache(struct target *target)
{
struct cortex_m_common *cortex_m = target_to_cm(target);
struct armv7m_common *armv7m = target_to_armv7m(target);
struct armv7m_cache_common *cache = &armv7m->armv7m_cache;
enum cortex_m_impl_part part = cortex_m->core_info->impl_part;
if (cache->info_valid)
return ERROR_OK;
if (cortex_m->core_info->impl_part == CORTEX_M7_PARTNO
if ((part == CORTEX_M7_PARTNO || part == CORTEX_M85_PARTNO)
&& cortex_m->dcb_dhcsr & S_RESET_ST) {
cache->defer_identification = true;
return ERROR_OK;