forked from auracaster/openocd
rename jtag_khz as adapter_khz
Globally rename "jtag_khz" as "adapter_khz", and move it out of the "jtag" command group ... it needs to be used with non-JTAG transports Includes a migration aid (in jtag/startup.tcl) so that old user scripts won't break. That aid should Sunset in about a year. (We may want to update it to include a nag message too.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This commit is contained in:
@@ -1,7 +1,7 @@
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jtag_khz 4
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adapter_khz 4
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######################################
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@@ -62,7 +62,7 @@ flash bank $_FLASHNAME cfi 0x10000000 0x01000000 2 2 $_TARGETNAME
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proc at91sam_init { } {
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# at reset chip runs at 32khz
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jtag_khz 8
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adapter_khz 8
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halt
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mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset
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mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
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@@ -79,7 +79,7 @@ proc at91sam_init { } {
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sleep 10 # wait 10 ms
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# Now run at anything fast... ie: 10mhz!
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jtag_khz 10000 # Increase JTAG Speed to 6 MHz
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adapter_khz 10000 # Increase JTAG Speed to 6 MHz
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arm7_9 dcc_downloads enable # Enable faster DCC downloads
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mww 0xffffec00 0x0a0a0a0a # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
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+1
-1
@@ -3,7 +3,7 @@
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# this script only configures one core (that is used to run Linux)
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# assume no PLL lock, start slowly
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jtag_khz 100
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adapter_khz 100
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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@@ -504,7 +504,7 @@ proc reboot {} {
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mww $TIMER_WDT_HIGH_BOUND 0xffffff
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mww $TIMER_WDT_CURRENT_COUNT 0x0
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puts "JTAG speed lowered to 100kHz"
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jtag_khz 100
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adapter_khz 100
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mww $TIMER_WDT_CONTROL 0x1
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# wait until the reset
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puts -nonewline "Wating for watchdog to trigger..."
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@@ -22,7 +22,7 @@ if { [info exists CPUTAPID ] } {
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}
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#jtag speed
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jtag_khz 4500
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adapter_khz 4500
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#has only srst
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reset_config srst_only
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@@ -13,7 +13,7 @@ if { [info exists CPUTAPID ] } {
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}
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# jtag speed
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jtag_khz 500
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adapter_khz 500
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jtag_nsrst_delay 100
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jtag_ntrst_delay 100
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@@ -27,7 +27,7 @@ reset_config trst_and_srst srst_pulls_trst
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jtag_nsrst_delay 100
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jtag_ntrst_delay 100
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jtag_khz 1000
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adapter_khz 1000
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#jtag scan chain
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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@@ -47,4 +47,4 @@ set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME lpc2000 0x0 0x0007D000 0 0 $_TARGETNAME lpc2000_v2 4000 calc_checksum
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# 4MHz / 6 = 666kHz, so use 500
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jtag_khz 500
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adapter_khz 500
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@@ -36,7 +36,7 @@ jtag_ntrst_delay 200
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# rclk hasn't been working well. This maybe the mc13224v or something else.
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#jtag_rclk 2000
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jtag_khz 2000
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adapter_khz 2000
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######################
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# Target configuration
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@@ -4,7 +4,7 @@
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set _ENDIAN little
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# jtag speed
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jtag_khz 4500
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adapter_khz 4500
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reset_config srst_only
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jtag_nsrst_delay 100
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@@ -27,7 +27,7 @@ flash bank $_FLASHNAME avr 0 0 0 0 $_TARGETNAME
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#to use it, script will be like:
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#init
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#jtag_khz 4500
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#adapter_khz 4500
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#reset init
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#verify_ircapture disable
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#
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@@ -28,8 +28,8 @@ target create $_TARGETNAME xscale -endian $_ENDIAN \
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# PXA255 comes out of reset using 3.6864 MHz oscillator.
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# Until the PLL kicks in, keep the JTAG clock slow enough
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# that we get no errors.
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jtag_khz 300
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$_TARGETNAME configure -event "reset-start" { jtag_khz 300 }
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adapter_khz 300
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$_TARGETNAME configure -event "reset-start" { adapter_khz 300 }
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# both TRST and SRST are *required* for debug
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# DCSR is often accessed with SRST active
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@@ -26,12 +26,12 @@ assumed that all write-protect mechanisms should be disabled.
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flash write_image [file] <parameters>
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verify_image [file] <parameters>
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4. jtag_khz sets the maximum speed (or alternatively RCLK). If invoked
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4. adapter_khz sets the maximum speed (or alternatively RCLK). If invoked
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multiple times only the last setting is used.
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interface/xxx.cfg files are always executed *before* target/xxx.cfg
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files, so any jtag_khz in interface/xxx.cfg will be overridden by
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target/xxx.cfg. jtag_khz in interface/xxx.cfg would then, effectively,
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files, so any adapter_khz in interface/xxx.cfg will be overridden by
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target/xxx.cfg. adapter_khz in interface/xxx.cfg would then, effectively,
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set the default JTAG speed.
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Note that a target/xxx.cfg file can invoke another target/yyy.cfg file,
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@@ -7,11 +7,11 @@
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#
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# RCLK?
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#
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# jtag_khz 0
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# adapter_khz 0
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#
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# Really low clock during reset?
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#
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# jtag_khz 1
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# adapter_khz 1
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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@@ -41,8 +41,8 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x2000
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# NOTE: this may be increased by a reset-init handler, after it
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# configures and enables the PLL. Or you might need to decrease
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# this, if you're using a slower clock.
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jtag_khz 500
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$_TARGETNAME configure -event reset-start {jtag_khz 500}
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adapter_khz 500
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$_TARGETNAME configure -event reset-start {adapter_khz 500}
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# flash configuration ... autodetects sizes, autoprobed
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flash bank $_CHIPNAME.flash stellaris 0 0 0 0 $_TARGETNAME
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@@ -21,7 +21,7 @@ if { [info exists WORKAREASIZE] } {
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}
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# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
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jtag_khz 1000
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adapter_khz 1000
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jtag_nsrst_delay 100
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jtag_ntrst_delay 100
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@@ -1,5 +1,5 @@
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#start slow, speed up after reset
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jtag_khz 10
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adapter_khz 10
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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@@ -29,9 +29,9 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_C
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
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$_TARGETNAME configure -event reset-start { jtag_khz 10 }
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$_TARGETNAME configure -event reset-start { adapter_khz 10 }
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$_TARGETNAME configure -event reset-init {
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jtag_khz 6000
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adapter_khz 6000
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# Because the hardware cannot be interrogated for the protection state
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# of sectors, initialize all the sectors to be unprotected. The initial
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@@ -1,6 +1,6 @@
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#STR730 CPU
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jtag_khz 3000
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adapter_khz 3000
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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@@ -33,9 +33,9 @@ jtag_ntrst_delay 500
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME arm7tdmi -endian little -chain-position 0 -variant arm7tdmi
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$_TARGETNAME configure -event reset-start { jtag_khz 10 }
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$_TARGETNAME configure -event reset-start { adapter_khz 10 }
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$_TARGETNAME configure -event reset-init {
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jtag_khz 3000
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adapter_khz 3000
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# Because the hardware cannot be interrogated for the protection state
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# of sectors, initialize all the sectors to be unprotected. The initial
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@@ -19,7 +19,7 @@ if { [info exists CPUTAPID] } {
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}
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# jtag speed
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jtag_khz 10
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adapter_khz 10
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#use combined on interfaces or targets that can't set TRST/SRST separately
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reset_config trst_and_srst srst_pulls_trst
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@@ -35,9 +35,9 @@ jtag_ntrst_delay 500
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME arm7tdmi -endian little -chain-position 0 -variant arm7tdmi
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$_TARGETNAME configure -event reset-start { jtag_khz 10 }
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$_TARGETNAME configure -event reset-start { adapter_khz 10 }
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$_TARGETNAME configure -event reset-init {
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jtag_khz 3000
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adapter_khz 3000
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# Because the hardware cannot be interrogated for the protection state
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# of sectors, initialize all the sectors to be unprotected. The initial
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+4
-4
@@ -26,12 +26,12 @@ reset_config trst_and_srst separate
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# issue telnet: reset init
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# issue gdb: monitor reset init
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$_TARGETNAME configure -event reset-init {
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jtag_khz 100
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adapter_khz 100
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# this will setup Telo board
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setupTelo
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#turn up the JTAG speed
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jtag_khz 3000
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puts "JTAG speek now 3MHz"
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adapter_khz 3000
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puts "JTAG speed now 3MHz"
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puts "type helpC100 to get help on C100"
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}
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@@ -58,4 +58,4 @@ set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME cfi 0x20000000 0x01000000 2 2 $_TARGETNAME
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# writing data to memory does not work without this
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memwrite burst disable
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memwrite burst disable
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