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Support AArch64 SIMD/FP registers read/write

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This patch adds support in openOCD to read/write AArch64 SIMD/FP registers.
This patch depends on a previous patch which adds support to generation 
of target xml by openOCD with nested architecture defined types. AArch64 
SIMD/FP registers assumes various types and to support all types we 
implement them as architecture defined type aarch64v which in turn 
consists of various architecture defined types. This is compatible with 
AArch64-FPU target xml in GDB. Please refer to 
binutils-gdb/gdb/features/aarch64-fpu.xml

Change-Id: I7ffb0c21b3c2e08f13720b765408b30aab2a9808
Signed-off-by: Omair Javaid <omair.javaid@linaro.org>
Reviewed-on: http://openocd.zylin.com/4373
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
This commit is contained in:
Omair Javaid
2018-01-22 03:26:01 +05:00
committed by Matthias Welwarsky
parent b4a01f8cdc
commit a48264414e
5 changed files with 404 additions and 85 deletions
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8
src/target/armv8_opcodes.h
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@@ -167,6 +167,14 @@
#define ARMV8_STRH_IP(Rd, Rn) (0x78002400 | (Rn << 5) | Rd)
#define ARMV8_STRW_IP(Rd, Rn) (0xb8004400 | (Rn << 5) | Rd)
#define ARMV8_MOV_GPR_VFP(Rd, Rn, Index) (0x4e083c00 | (Index << 20) | (Rn << 5) | Rd)
#define ARMV8_MOV_VFP_GPR(Rd, Rn, Index) (0x4e081c00 | (Index << 20) | (Rn << 5) | Rd)
#define ARMV8_MRS_FPCR(Rt) (0xd53b4400 | (Rt))
#define ARMV8_MRS_FPSR(Rt) (0xd53b4420 | (Rt))
#define ARMV8_MSR_FPCR(Rt) (0xd51b4400 | (Rt))
#define ARMV8_MSR_FPSR(Rt) (0xd51b4420 | (Rt))
#define ARMV8_SYS(System, Rt) (0xD5080000 | ((System) << 5) | Rt)
enum armv8_opcode {