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Add RISC-V support.

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This supports both 0.11 and 0.13 versions of the debug spec.

Support for `-rtos riscv` will come in a separate commit since it was
easy to separate out, and is likely to be more controversial.

Flash support for the SiFive boards will also come in a later commit.

Change-Id: I1d38fe669c2041b4e21a5c54a091594aac3e2190
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/4578
Tested-by: jenkins
Reviewed-by: Liviu Ionescu <ilg@livius.net>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
This commit is contained in:
Tim Newsome
2018-07-18 13:34:23 -07:00
committed by Matthias Welwarsky
parent 9363705820
commit a51ab8ddf6
22 changed files with 12313 additions and 1 deletions
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2
src/target/target.c
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@@ -107,6 +107,7 @@ extern struct target_type or1k_target;
extern struct target_type quark_x10xx_target;
extern struct target_type quark_d20xx_target;
extern struct target_type stm8_target;
extern struct target_type riscv_target;
static struct target_type *target_types[] = {
&arm7tdmi_target,
@@ -139,6 +140,7 @@ static struct target_type *target_types[] = {
&quark_x10xx_target,
&quark_d20xx_target,
&stm8_target,
&riscv_target,
#if BUILD_TARGET64
&aarch64_target,
#endif