forked from auracaster/openocd
tcl/target/stm32wba5x: Fix wrong addresses
According to ST Reference Manual RM093 Rev 7: - OTP is 0x0BF90000 2.3.2 Memory map and register boundary addresses, page 84 - DBGMCU registers starts at 0xE0044000 43.5.1 System debug ROM table, page 1736 Change-Id: I735c6184d9f3fd767d9d776b238e88fcfbe8cc8d Signed-off-by: Guillaume Faussard <guillaume.faussard@withings.com> Reviewed-on: https://review.openocd.org/c/openocd/+/9328 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins Reviewed-by: Ahmed Haoues <ahmed.haoues@st.com>
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committed by
Antonio Borneo
parent
dab933b3ae
commit
b074fea079
@@ -755,7 +755,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
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| F_WRP_HAS_LOCK,
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.flash_regs_base = 0x40022000,
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.fsize_addr = 0x0FF907A0,
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.otp_base = 0x0FF90000,
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.otp_base = 0x0BF90000,
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.otp_size = 512,
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},
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{
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@@ -47,7 +47,7 @@ target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap -ap-num 1
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
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flash bank $_CHIPNAME.otp stm32l4x 0x0FF90000 0 0 0 $_TARGETNAME
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flash bank $_CHIPNAME.otp stm32l4x 0x0bf90000 0 0 0 $_TARGETNAME
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# Common knowledges tells JTAG speed should be <= F_CPU/6.
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# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
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@@ -88,12 +88,12 @@ $_TARGETNAME configure -event reset-start {
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$_TARGETNAME configure -event examine-end {
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# Enable debug during low power modes (uses more power)
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# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
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mmw 0xE0042004 0x00000006 0
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# DBGMCU_SCR |= DBG_STANDBY | DBG_STOP
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mmw 0xE0044004 0x00000006 0
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# Stop watchdog counters during halt
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# DBGMCU_APB1LFZR |= DBG_IWDG_STOP | DBG_WWDG_STOP
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mmw 0xE0042008 0x00001800 0
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mmw 0xE0044008 0x00001800 0
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}
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tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
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