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target/arvm7a: Use 'bool' data type where appropriate

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The variables are already used as boolean value but have the wrong
data type.

Change-Id: I0f169cac83f6c4094e8d1acb2cb8f1017a96a5d8
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/9008
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
This commit is contained in:
Marc Schink
2025-07-21 06:52:24 +00:00
committed by Antonio Borneo
parent c2b8f994bf
commit b4d05b6e72
5 changed files with 10 additions and 10 deletions
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10
src/target/armv7a.c
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@@ -139,7 +139,7 @@ int armv7a_read_ttbcr(struct target *target)
ttbcr_n = ttbcr & 0x7;
armv7a->armv7a_mmu.ttbcr = ttbcr;
armv7a->armv7a_mmu.cached = 1;
armv7a->armv7a_mmu.cached = true;
for (ttbidx = 0; ttbidx < 2; ttbidx++) {
/* MRC p15,0,<Rt>,c2,c0,ttbidx */
@@ -158,7 +158,7 @@ int armv7a_read_ttbcr(struct target *target)
armv7a->armv7a_mmu.ttbr_range[1] = 0xffffffff;
armv7a->armv7a_mmu.ttbr_mask[0] = 0xffffffff << (14 - ttbcr_n);
armv7a->armv7a_mmu.ttbr_mask[1] = 0xffffffff << 14;
armv7a->armv7a_mmu.cached = 1;
armv7a->armv7a_mmu.cached = true;
retval = armv7a_read_midr(target);
if (retval != ERROR_OK)
@@ -187,7 +187,7 @@ int armv7a_handle_cache_info_command(struct command_invocation *cmd,
int cl;
if (armv7a_cache->info == -1) {
if (!armv7a_cache->info_valid) {
command_print(cmd, "cache not yet identified");
return ERROR_OK;
}
@@ -427,7 +427,7 @@ int armv7a_identify_cache(struct target *target)
armv7a_cache_flush_all_data;
}
armv7a->armv7a_mmu.armv7a_cache.info = 1;
armv7a->armv7a_mmu.armv7a_cache.info_valid = true;
done:
dpm->finish(dpm);
armv7a_read_mpidr(target);
@@ -473,7 +473,7 @@ int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a)
armv7a->arm.target = target;
armv7a->arm.common_magic = ARM_COMMON_MAGIC;
armv7a->common_magic = ARMV7_COMMON_MAGIC;
armv7a->armv7a_mmu.armv7a_cache.info = -1;
armv7a->armv7a_mmu.armv7a_cache.info_valid = false;
armv7a->armv7a_mmu.armv7a_cache.outer_cache = NULL;
armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache = NULL;
return ERROR_OK;

4
src/target/armv7a.h
View File

@@ -58,7 +58,7 @@ struct armv7a_arch_cache {
/* common cache information */
struct armv7a_cache_common {
int info; /* -1 invalid, else valid */
bool info_valid;
int loc; /* level of coherency */
uint32_t dminline; /* minimum d-cache linelen */
uint32_t iminline; /* minimum i-cache linelen */
@@ -72,7 +72,7 @@ struct armv7a_cache_common {
struct armv7a_mmu_common {
/* following field mmu working way */
int32_t cached; /* 0: not initialized, 1: initialized */
bool cached;
uint32_t ttbcr; /* cache for ttbcr register */
uint32_t ttbr[2];
uint32_t ttbr_mask[2];

2
src/target/armv7a_cache_l2x.c
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@@ -168,7 +168,7 @@ static int arm7a_handle_l2x_cache_info_command(struct command_invocation *cmd,
{
struct armv7a_l2x_cache *l2x_cache = armv7a_cache->outer_cache;
if (armv7a_cache->info == -1) {
if (!armv7a_cache->info_valid) {
command_print(cmd, "cache not yet identified");
return ERROR_OK;
}

2
src/target/armv7a_mmu.c
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@@ -214,7 +214,7 @@ COMMAND_HANDLER(armv7a_mmu_dump_table)
max_pt_idx -= 1;
}
} else {
if (mmu->cached != 1) {
if (!mmu->cached) {
LOG_ERROR("TTB not cached!");
return ERROR_FAIL;
}

2
src/target/cortex_a.c
View File

@@ -1118,7 +1118,7 @@ static int cortex_a_post_debug_entry(struct target *target)
if (!armv7a->is_armv7r)
armv7a_read_ttbcr(target);
if (armv7a->armv7a_mmu.armv7a_cache.info == -1)
if (!armv7a->armv7a_mmu.armv7a_cache.info_valid)
armv7a_identify_cache(target);
if (armv7a->is_armv7r) {