auracaster/sw_openocd
3
0
Fork 0
forked from auracaster/openocd
Code Pull Requests Activity

target: riscv: align switch and case statements

Browse Source 
The coding style requires the 'case' to be at the same indentation
level of its 'switch' statement.

Align the code accordingly.

While there, put at newline the command after the 'case'.

No changes are reported by
	git log -p -w --ignore-blank-lines --patience
apart from the newline after 'case'.

Change-Id: Id856e24100de6fb0442afe8bc51545b0138ef02d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9069
Tested-by: jenkins
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit is contained in:
Antonio Borneo
2025-08-02 19:33:37 +02:00
committed by Tomas Vanek
parent 56141bb349
commit bd303d6a3d
5 changed files with 891 additions and 885 deletions
Download Patch File Download Diff File Expand all files Collapse all files

512
src/target/riscv/riscv-011.c
View File

@@ -230,19 +230,25 @@ static unsigned int slot_offset(const struct target *target, slot_t slot)
{ {
riscv011_info_t *info = get_info(target); riscv011_info_t *info = get_info(target);
switch (riscv_xlen(target)) { switch (riscv_xlen(target)) {
case 32: case 32:
switch (slot) { switch (slot) {
case SLOT0: return 4; case SLOT0:
case SLOT1: return 5; return 4;
case SLOT_LAST: return info->dramsize-1; case SLOT1:
} return 5;
break; case SLOT_LAST:
case 64: return info->dramsize - 1;
switch (slot) { }
case SLOT0: return 4; break;
case SLOT1: return 6; case 64:
case SLOT_LAST: return info->dramsize-2; switch (slot) {
} case SLOT0:
return 4;
case SLOT1:
return 6;
case SLOT_LAST:
return info->dramsize - 2;
}
} }
LOG_ERROR("slot_offset called with xlen=%d, slot=%d", LOG_ERROR("slot_offset called with xlen=%d, slot=%d",
riscv_xlen(target), slot); riscv_xlen(target), slot);
@@ -254,10 +260,10 @@ static uint32_t load(const struct target *target, unsigned int rd,
unsigned int base, int16_t offset) unsigned int base, int16_t offset)
{ {
switch (riscv_xlen(target)) { switch (riscv_xlen(target)) {
case 32: case 32:
return lw(rd, base, offset); return lw(rd, base, offset);
case 64: case 64:
return ld(rd, base, offset); return ld(rd, base, offset);
} }
assert(0); assert(0);
return 0; /* Silence -Werror=return-type */ return 0; /* Silence -Werror=return-type */
@@ -267,10 +273,10 @@ static uint32_t store(const struct target *target, unsigned int src,
unsigned int base, int16_t offset) unsigned int base, int16_t offset)
{ {
switch (riscv_xlen(target)) { switch (riscv_xlen(target)) {
case 32: case 32:
return sw(src, base, offset); return sw(src, base, offset);
case 64: case 64:
return sd(src, base, offset); return sd(src, base, offset);
} }
assert(0); assert(0);
return 0; /* Silence -Werror=return-type */ return 0; /* Silence -Werror=return-type */
@@ -641,13 +647,13 @@ static void scans_add_read(scans_t *scans, slot_t slot, bool set_interrupt)
{ {
const struct target *target = scans->target; const struct target *target = scans->target;
switch (riscv_xlen(target)) { switch (riscv_xlen(target)) {
case 32: case 32:
scans_add_read32(scans, slot_offset(target, slot), set_interrupt); scans_add_read32(scans, slot_offset(target, slot), set_interrupt);
break; break;
case 64: case 64:
scans_add_read32(scans, slot_offset(target, slot), false); scans_add_read32(scans, slot_offset(target, slot), false);
scans_add_read32(scans, slot_offset(target, slot) + 1, set_interrupt); scans_add_read32(scans, slot_offset(target, slot) + 1, set_interrupt);
break; break;
} }
} }
@@ -906,19 +912,19 @@ static int cache_write(struct target *target, unsigned int address, bool run)
dbus_status_t status = scans_get_u32(scans, i, DBUS_OP_START, dbus_status_t status = scans_get_u32(scans, i, DBUS_OP_START,
DBUS_OP_SIZE); DBUS_OP_SIZE);
switch (status) { switch (status) {
case DBUS_STATUS_SUCCESS: case DBUS_STATUS_SUCCESS:
break; break;
case DBUS_STATUS_FAILED: case DBUS_STATUS_FAILED:
LOG_ERROR("Debug RAM write failed. Hardware error?"); LOG_ERROR("Debug RAM write failed. Hardware error?");
scans_delete(scans); scans_delete(scans);
return ERROR_FAIL; return ERROR_FAIL;
case DBUS_STATUS_BUSY: case DBUS_STATUS_BUSY:
errors++; errors++;
break; break;
default: default:
LOG_ERROR("Got invalid bus access status: %d", status); LOG_ERROR("Got invalid bus access status: %d", status);
scans_delete(scans); scans_delete(scans);
return ERROR_FAIL; return ERROR_FAIL;
} }
} }
@@ -1680,17 +1686,17 @@ static riscv_error_t handle_halt_routine(struct target *target)
uint32_t address = scans_get_u32(scans, i, DBUS_ADDRESS_START, uint32_t address = scans_get_u32(scans, i, DBUS_ADDRESS_START,
info->addrbits); info->addrbits);
switch (status) { switch (status) {
case DBUS_STATUS_SUCCESS: case DBUS_STATUS_SUCCESS:
break; break;
case DBUS_STATUS_FAILED: case DBUS_STATUS_FAILED:
LOG_ERROR("Debug access failed. Hardware error?"); LOG_ERROR("Debug access failed. Hardware error?");
goto error; goto error;
case DBUS_STATUS_BUSY: case DBUS_STATUS_BUSY:
dbus_busy++; dbus_busy++;
break; break;
default: default:
LOG_ERROR("Got invalid bus access status: %d", status); LOG_ERROR("Got invalid bus access status: %d", status);
goto error; goto error;
} }
if (data & DMCONTROL_INTERRUPT) { if (data & DMCONTROL_INTERRUPT) {
interrupt_set++; interrupt_set++;
@@ -1699,111 +1705,111 @@ static riscv_error_t handle_halt_routine(struct target *target)
if (address == 4 || address == 5) { if (address == 4 || address == 5) {
unsigned int reg; unsigned int reg;
switch (result) { switch (result) {
case 0: case 0:
reg = 1; reg = 1;
break; break;
case 1: case 1:
reg = 2; reg = 2;
break; break;
case 2: case 2:
reg = 3; reg = 3;
break; break;
case 3: case 3:
reg = 4; reg = 4;
break; break;
case 4: case 4:
reg = 5; reg = 5;
break; break;
case 5: case 5:
reg = 6; reg = 6;
break; break;
case 6: case 6:
reg = 7; reg = 7;
break; break;
/* S0 */ /* S0 */
/* S1 */ /* S1 */
case 7: case 7:
reg = 10; reg = 10;
break; break;
case 8: case 8:
reg = 11; reg = 11;
break; break;
case 9: case 9:
reg = 12; reg = 12;
break; break;
case 10: case 10:
reg = 13; reg = 13;
break; break;
case 11: case 11:
reg = 14; reg = 14;
break; break;
case 12: case 12:
reg = 15; reg = 15;
break; break;
case 13: case 13:
reg = 16; reg = 16;
break; break;
case 14: case 14:
reg = 17; reg = 17;
break; break;
case 15: case 15:
reg = 18; reg = 18;
break; break;
case 16: case 16:
reg = 19; reg = 19;
break; break;
case 17: case 17:
reg = 20; reg = 20;
break; break;
case 18: case 18:
reg = 21; reg = 21;
break; break;
case 19: case 19:
reg = 22; reg = 22;
break; break;
case 20: case 20:
reg = 23; reg = 23;
break; break;
case 21: case 21:
reg = 24; reg = 24;
break; break;
case 22: case 22:
reg = 25; reg = 25;
break; break;
case 23: case 23:
reg = 26; reg = 26;
break; break;
case 24: case 24:
reg = 27; reg = 27;
break; break;
case 25: case 25:
reg = 28; reg = 28;
break; break;
case 26: case 26:
reg = 29; reg = 29;
break; break;
case 27: case 27:
reg = 30; reg = 30;
break; break;
case 28: case 28:
reg = 31; reg = 31;
break; break;
case 29: case 29:
reg = S1; reg = S1;
break; break;
case 30: case 30:
reg = S0; reg = S0;
break; break;
case 31: case 31:
reg = GDB_REGNO_DPC; reg = GDB_REGNO_DPC;
break; break;
case 32: case 32:
reg = GDB_REGNO_DCSR; reg = GDB_REGNO_DCSR;
break; break;
default: default:
assert(0); assert(0);
LOG_ERROR("Got invalid register result %d", result); LOG_ERROR("Got invalid register result %d", result);
goto error; goto error;
} }
if (riscv_xlen(target) == 32) { if (riscv_xlen(target) == 32) {
reg_cache_set(target, reg, data & 0xffffffff); reg_cache_set(target, reg, data & 0xffffffff);
@@ -1860,22 +1866,22 @@ static int handle_halt(struct target *target, bool announce)
int cause = get_field(info->dcsr, DCSR_CAUSE); int cause = get_field(info->dcsr, DCSR_CAUSE);
switch (cause) { switch (cause) {
case DCSR_CAUSE_SWBP: case DCSR_CAUSE_SWBP:
target->debug_reason = DBG_REASON_BREAKPOINT; target->debug_reason = DBG_REASON_BREAKPOINT;
break; break;
case DCSR_CAUSE_HWBP: case DCSR_CAUSE_HWBP:
target->debug_reason = DBG_REASON_WATCHPOINT; target->debug_reason = DBG_REASON_WATCHPOINT;
break; break;
case DCSR_CAUSE_DEBUGINT: case DCSR_CAUSE_DEBUGINT:
target->debug_reason = DBG_REASON_DBGRQ; target->debug_reason = DBG_REASON_DBGRQ;
break; break;
case DCSR_CAUSE_STEP: case DCSR_CAUSE_STEP:
target->debug_reason = DBG_REASON_SINGLESTEP; target->debug_reason = DBG_REASON_SINGLESTEP;
break; break;
case DCSR_CAUSE_HALT: case DCSR_CAUSE_HALT:
default: default:
LOG_ERROR("Invalid halt cause %d in DCSR (0x%" PRIx64 ")", LOG_ERROR("Invalid halt cause %d in DCSR (0x%" PRIx64 ")",
cause, info->dcsr); cause, info->dcsr);
} }
if (info->never_halted) { if (info->never_halted) {
@@ -2032,21 +2038,21 @@ static int read_memory(struct target *target, const struct riscv_mem_access_args
cache_set32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16)); cache_set32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16));
switch (size) { switch (size) {
case 1: case 1:
cache_set32(target, 1, lb(S1, S0, 0)); cache_set32(target, 1, lb(S1, S0, 0));
cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16)); cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
break; break;
case 2: case 2:
cache_set32(target, 1, lh(S1, S0, 0)); cache_set32(target, 1, lh(S1, S0, 0));
cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16)); cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
break; break;
case 4: case 4:
cache_set32(target, 1, lw(S1, S0, 0)); cache_set32(target, 1, lw(S1, S0, 0));
cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16)); cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
break; break;
default: default:
LOG_ERROR("Unsupported size: %d", size); LOG_ERROR("Unsupported size: %d", size);
return ERROR_FAIL; return ERROR_FAIL;
} }
cache_set_jump(target, 3); cache_set_jump(target, 3);
cache_write(target, CACHE_NO_READ, false); cache_write(target, CACHE_NO_READ, false);
@@ -2089,17 +2095,17 @@ static int read_memory(struct target *target, const struct riscv_mem_access_args
dbus_status_t status = scans_get_u32(scans, j, DBUS_OP_START, dbus_status_t status = scans_get_u32(scans, j, DBUS_OP_START,
DBUS_OP_SIZE); DBUS_OP_SIZE);
switch (status) { switch (status) {
case DBUS_STATUS_SUCCESS: case DBUS_STATUS_SUCCESS:
break; break;
case DBUS_STATUS_FAILED: case DBUS_STATUS_FAILED:
LOG_ERROR("Debug RAM write failed. Hardware error?"); LOG_ERROR("Debug RAM write failed. Hardware error?");
goto error; goto error;
case DBUS_STATUS_BUSY: case DBUS_STATUS_BUSY:
dbus_busy++; dbus_busy++;
break; break;
default: default:
LOG_ERROR("Got invalid bus access status: %d", status); LOG_ERROR("Got invalid bus access status: %d", status);
return ERROR_FAIL; return ERROR_FAIL;
} }
uint64_t data = scans_get_u64(scans, j, DBUS_DATA_START, uint64_t data = scans_get_u64(scans, j, DBUS_DATA_START,
DBUS_DATA_SIZE); DBUS_DATA_SIZE);
@@ -2110,19 +2116,19 @@ static int read_memory(struct target *target, const struct riscv_mem_access_args
} else if (i + j > 1) { } else if (i + j > 1) {
uint32_t offset = size * (i + j - 2); uint32_t offset = size * (i + j - 2);
switch (size) { switch (size) {
case 1: case 1:
buffer[offset] = data; buffer[offset] = data;
break; break;
case 2: case 2:
buffer[offset] = data; buffer[offset] = data;
buffer[offset+1] = data >> 8; buffer[offset + 1] = data >> 8;
break; break;
case 4: case 4:
buffer[offset] = data; buffer[offset] = data;
buffer[offset+1] = data >> 8; buffer[offset + 1] = data >> 8;
buffer[offset+2] = data >> 16; buffer[offset + 2] = data >> 16;
buffer[offset+3] = data >> 24; buffer[offset + 3] = data >> 24;
break; break;
} }
} }
LOG_DEBUG("j=%d status=%d data=%09" PRIx64, j, status, data); LOG_DEBUG("j=%d status=%d data=%09" PRIx64, j, status, data);
@@ -2167,21 +2173,21 @@ error:
static int setup_write_memory(struct target *target, uint32_t size) static int setup_write_memory(struct target *target, uint32_t size)
{ {
switch (size) { switch (size) {
case 1: case 1:
cache_set32(target, 0, lb(S0, ZERO, DEBUG_RAM_START + 16)); cache_set32(target, 0, lb(S0, ZERO, DEBUG_RAM_START + 16));
cache_set32(target, 1, sb(S0, T0, 0)); cache_set32(target, 1, sb(S0, T0, 0));
break; break;
case 2: case 2:
cache_set32(target, 0, lh(S0, ZERO, DEBUG_RAM_START + 16)); cache_set32(target, 0, lh(S0, ZERO, DEBUG_RAM_START + 16));
cache_set32(target, 1, sh(S0, T0, 0)); cache_set32(target, 1, sh(S0, T0, 0));
break; break;
case 4: case 4:
cache_set32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16)); cache_set32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16));
cache_set32(target, 1, sw(S0, T0, 0)); cache_set32(target, 1, sw(S0, T0, 0));
break; break;
default: default:
LOG_ERROR("Unsupported size: %d", size); LOG_ERROR("Unsupported size: %d", size);
return ERROR_FAIL; return ERROR_FAIL;
} }
cache_set32(target, 2, addi(T0, T0, size)); cache_set32(target, 2, addi(T0, T0, size));
cache_set_jump(target, 3); cache_set_jump(target, 3);
@@ -2241,21 +2247,21 @@ static int write_memory(struct target *target, const struct riscv_mem_access_arg
uint32_t value; uint32_t value;
uint32_t offset = size * (i + j); uint32_t offset = size * (i + j);
switch (size) { switch (size) {
case 1: case 1:
value = buffer[offset]; value = buffer[offset];
break; break;
case 2: case 2:
value = buffer[offset] | value = buffer[offset] |
(buffer[offset+1] << 8); (buffer[offset + 1] << 8);
break; break;
case 4: case 4:
value = buffer[offset] | value = buffer[offset] |
((uint32_t) buffer[offset+1] << 8) | ((uint32_t)buffer[offset + 1] << 8) |
((uint32_t) buffer[offset+2] << 16) | ((uint32_t)buffer[offset + 2] << 16) |
((uint32_t) buffer[offset+3] << 24); ((uint32_t)buffer[offset + 3] << 24);
break; break;
default: default:
goto error; goto error;
} }
scans_add_write32(scans, 4, value, true); scans_add_write32(scans, 4, value, true);
@@ -2274,17 +2280,17 @@ static int write_memory(struct target *target, const struct riscv_mem_access_arg
dbus_status_t status = scans_get_u32(scans, j, DBUS_OP_START, dbus_status_t status = scans_get_u32(scans, j, DBUS_OP_START,
DBUS_OP_SIZE); DBUS_OP_SIZE);
switch (status) { switch (status) {
case DBUS_STATUS_SUCCESS: case DBUS_STATUS_SUCCESS:
break; break;
case DBUS_STATUS_FAILED: case DBUS_STATUS_FAILED:
LOG_ERROR("Debug RAM write failed. Hardware error?"); LOG_ERROR("Debug RAM write failed. Hardware error?");
goto error; goto error;
case DBUS_STATUS_BUSY: case DBUS_STATUS_BUSY:
dbus_busy++; dbus_busy++;
break; break;
default: default:
LOG_ERROR("Got invalid bus access status: %d", status); LOG_ERROR("Got invalid bus access status: %d", status);
return ERROR_FAIL; return ERROR_FAIL;
} }
int interrupt = scans_get_u32(scans, j, DBUS_DATA_START + 33, 1); int interrupt = scans_get_u32(scans, j, DBUS_DATA_START + 33, 1);
if (interrupt) if (interrupt)

314
src/target/riscv/riscv-013.c
View File

@@ -592,15 +592,15 @@ static int increase_ac_busy_delay(struct target *target)
static uint32_t __attribute__((unused)) abstract_register_size(unsigned int width) static uint32_t __attribute__((unused)) abstract_register_size(unsigned int width)
{ {
switch (width) { switch (width) {
case 32: case 32:
return set_field(0, AC_ACCESS_REGISTER_AARSIZE, 2); return set_field(0, AC_ACCESS_REGISTER_AARSIZE, 2);
case 64: case 64:
return set_field(0, AC_ACCESS_REGISTER_AARSIZE, 3); return set_field(0, AC_ACCESS_REGISTER_AARSIZE, 3);
case 128: case 128:
return set_field(0, AC_ACCESS_REGISTER_AARSIZE, 4); return set_field(0, AC_ACCESS_REGISTER_AARSIZE, 4);
default: default:
LOG_ERROR("Unsupported register width: %d", width); LOG_ERROR("Unsupported register width: %d", width);
return 0; return 0;
} }
} }
@@ -737,12 +737,12 @@ int riscv013_execute_abstract_command(struct target *target, uint32_t command,
*cmderr = CMDERR_NONE; *cmderr = CMDERR_NONE;
if (debug_level >= LOG_LVL_DEBUG) { if (debug_level >= LOG_LVL_DEBUG) {
switch (get_field(command, DM_COMMAND_CMDTYPE)) { switch (get_field(command, DM_COMMAND_CMDTYPE)) {
case 0: case 0:
LOG_DEBUG_REG(target, AC_ACCESS_REGISTER, command); LOG_DEBUG_REG(target, AC_ACCESS_REGISTER, command);
break; break;
default: default:
LOG_TARGET_DEBUG(target, "command=0x%x", command); LOG_TARGET_DEBUG(target, "command=0x%x", command);
break; break;
} }
} }
@@ -854,14 +854,14 @@ static int write_abstract_arg(struct target *target, unsigned int index,
{ {
unsigned int offset = index * size_bits / 32; unsigned int offset = index * size_bits / 32;
switch (size_bits) { switch (size_bits) {
default: default:
LOG_TARGET_ERROR(target, "Unsupported size: %d bits", size_bits); LOG_TARGET_ERROR(target, "Unsupported size: %d bits", size_bits);
return ERROR_FAIL; return ERROR_FAIL;
case 64: case 64:
dm_write(target, DM_DATA0 + offset + 1, (uint32_t)(value >> 32)); dm_write(target, DM_DATA0 + offset + 1, (uint32_t)(value >> 32));
/* falls through */ /* falls through */
case 32: case 32:
dm_write(target, DM_DATA0 + offset, (uint32_t)value); dm_write(target, DM_DATA0 + offset, (uint32_t)value);
} }
return ERROR_OK; return ERROR_OK;
} }
@@ -874,16 +874,16 @@ uint32_t riscv013_access_register_command(struct target *target, uint32_t number
{ {
uint32_t command = set_field(0, DM_COMMAND_CMDTYPE, 0); uint32_t command = set_field(0, DM_COMMAND_CMDTYPE, 0);
switch (size) { switch (size) {
case 32: case 32:
command = set_field(command, AC_ACCESS_REGISTER_AARSIZE, 2); command = set_field(command, AC_ACCESS_REGISTER_AARSIZE, 2);
break; break;
case 64: case 64:
command = set_field(command, AC_ACCESS_REGISTER_AARSIZE, 3); command = set_field(command, AC_ACCESS_REGISTER_AARSIZE, 3);
break; break;
default: default:
LOG_TARGET_ERROR(target, "%d-bit register %s not supported.", LOG_TARGET_ERROR(target, "%d-bit register %s not supported.",
size, riscv_reg_gdb_regno_name(target, number)); size, riscv_reg_gdb_regno_name(target, number));
assert(0); assert(0);
} }
if (number <= GDB_REGNO_XPR31) { if (number <= GDB_REGNO_XPR31) {
@@ -1003,19 +1003,19 @@ cleanup:
static uint32_t abstract_memory_size(unsigned int width) static uint32_t abstract_memory_size(unsigned int width)
{ {
switch (width) { switch (width) {
case 8: case 8:
return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 0); return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 0);
case 16: case 16:
return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 1); return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 1);
case 32: case 32:
return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 2); return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 2);
case 64: case 64:
return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 3); return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 3);
case 128: case 128:
return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 4); return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 4);
default: default:
LOG_ERROR("Unsupported memory width: %d", width); LOG_ERROR("Unsupported memory width: %d", width);
return 0; return 0;
} }
} }
@@ -1251,38 +1251,38 @@ static int scratch_read64(struct target *target, scratch_mem_t *scratch,
{ {
uint32_t v; uint32_t v;
switch (scratch->memory_space) { switch (scratch->memory_space) {
case SPACE_DM_DATA: case SPACE_DM_DATA:
if (dm_read(target, &v, DM_DATA0 + scratch->debug_address) != ERROR_OK) if (dm_read(target, &v, DM_DATA0 + scratch->debug_address) != ERROR_OK)
return ERROR_FAIL;
*value = v;
if (dm_read(target, &v, DM_DATA1 + scratch->debug_address) != ERROR_OK)
return ERROR_FAIL;
*value |= ((uint64_t)v) << 32;
break;
case SPACE_DMI_PROGBUF:
if (dm_read(target, &v, DM_PROGBUF0 + scratch->debug_address) != ERROR_OK)
return ERROR_FAIL;
*value = v;
if (dm_read(target, &v, DM_PROGBUF1 + scratch->debug_address) != ERROR_OK)
return ERROR_FAIL;
*value |= ((uint64_t)v) << 32;
break;
case SPACE_DMI_RAM:
{
uint8_t buffer[8] = {0};
const struct riscv_mem_access_args args = {
.address = scratch->debug_address,
.read_buffer = buffer,
.size = 4,
.count = 2,
.increment = 4,
};
if (riscv013_access_memory(target, args) != ERROR_OK)
return ERROR_FAIL; return ERROR_FAIL;
*value = v; *value = buf_get_u64(buffer,
if (dm_read(target, &v, DM_DATA1 + scratch->debug_address) != ERROR_OK) /* first = */ 0, /* bit_num = */ 64);
return ERROR_FAIL; }
*value |= ((uint64_t) v) << 32; break;
break;
case SPACE_DMI_PROGBUF:
if (dm_read(target, &v, DM_PROGBUF0 + scratch->debug_address) != ERROR_OK)
return ERROR_FAIL;
*value = v;
if (dm_read(target, &v, DM_PROGBUF1 + scratch->debug_address) != ERROR_OK)
return ERROR_FAIL;
*value |= ((uint64_t) v) << 32;
break;
case SPACE_DMI_RAM:
{
uint8_t buffer[8] = {0};
const struct riscv_mem_access_args args = {
.address = scratch->debug_address,
.read_buffer = buffer,
.size = 4,
.count = 2,
.increment = 4,
};
if (riscv013_access_memory(target, args) != ERROR_OK)
return ERROR_FAIL;
*value = buf_get_u64(buffer,
/* first = */ 0, /* bit_num = */ 64);
}
break;
} }
return ERROR_OK; return ERROR_OK;
} }
@@ -1291,38 +1291,38 @@ static int scratch_write64(struct target *target, scratch_mem_t *scratch,
uint64_t value) uint64_t value)
{ {
switch (scratch->memory_space) { switch (scratch->memory_space) {
case SPACE_DM_DATA: case SPACE_DM_DATA:
dm_write(target, DM_DATA0 + scratch->debug_address, (uint32_t)value); dm_write(target, DM_DATA0 + scratch->debug_address, (uint32_t)value);
dm_write(target, DM_DATA1 + scratch->debug_address, (uint32_t)(value >> 32)); dm_write(target, DM_DATA1 + scratch->debug_address, (uint32_t)(value >> 32));
break; break;
case SPACE_DMI_PROGBUF: case SPACE_DMI_PROGBUF:
dm_write(target, DM_PROGBUF0 + scratch->debug_address, (uint32_t)value); dm_write(target, DM_PROGBUF0 + scratch->debug_address, (uint32_t)value);
dm_write(target, DM_PROGBUF1 + scratch->debug_address, (uint32_t)(value >> 32)); dm_write(target, DM_PROGBUF1 + scratch->debug_address, (uint32_t)(value >> 32));
riscv013_invalidate_cached_progbuf(target); riscv013_invalidate_cached_progbuf(target);
break; break;
case SPACE_DMI_RAM: case SPACE_DMI_RAM:
{ {
uint8_t buffer[8] = { uint8_t buffer[8] = {
value, value,
value >> 8, value >> 8,
value >> 16, value >> 16,
value >> 24, value >> 24,
value >> 32, value >> 32,
value >> 40, value >> 40,
value >> 48, value >> 48,
value >> 56 value >> 56
}; };
const struct riscv_mem_access_args args = { const struct riscv_mem_access_args args = {
.address = scratch->debug_address, .address = scratch->debug_address,
.write_buffer = buffer, .write_buffer = buffer,
.size = 4, .size = 4,
.count = 2, .count = 2,
.increment = 4, .increment = 4,
}; };
if (riscv013_access_memory(target, args) != ERROR_OK) if (riscv013_access_memory(target, args) != ERROR_OK)
return ERROR_FAIL; return ERROR_FAIL;
} }
break; break;
} }
return ERROR_OK; return ERROR_OK;
} }
@@ -2451,16 +2451,16 @@ int riscv013_set_register_buf(struct target *target, enum gdb_regno regno,
static uint32_t sb_sbaccess(unsigned int size_bytes) static uint32_t sb_sbaccess(unsigned int size_bytes)
{ {
switch (size_bytes) { switch (size_bytes) {
case 1: case 1:
return set_field(0, DM_SBCS_SBACCESS, 0); return set_field(0, DM_SBCS_SBACCESS, 0);
case 2: case 2:
return set_field(0, DM_SBCS_SBACCESS, 1); return set_field(0, DM_SBCS_SBACCESS, 1);
case 4: case 4:
return set_field(0, DM_SBCS_SBACCESS, 2); return set_field(0, DM_SBCS_SBACCESS, 2);
case 8: case 8:
return set_field(0, DM_SBCS_SBACCESS, 3); return set_field(0, DM_SBCS_SBACCESS, 3);
case 16: case 16:
return set_field(0, DM_SBCS_SBACCESS, 4); return set_field(0, DM_SBCS_SBACCESS, 4);
} }
assert(0); assert(0);
return 0; return 0;
@@ -2581,18 +2581,18 @@ static int sba_supports_access(struct target *target, unsigned int size_bytes)
{ {
RISCV013_INFO(info); RISCV013_INFO(info);
switch (size_bytes) { switch (size_bytes) {
case 1: case 1:
return get_field(info->sbcs, DM_SBCS_SBACCESS8); return get_field(info->sbcs, DM_SBCS_SBACCESS8);
case 2: case 2:
return get_field(info->sbcs, DM_SBCS_SBACCESS16); return get_field(info->sbcs, DM_SBCS_SBACCESS16);
case 4: case 4:
return get_field(info->sbcs, DM_SBCS_SBACCESS32); return get_field(info->sbcs, DM_SBCS_SBACCESS32);
case 8: case 8:
return get_field(info->sbcs, DM_SBCS_SBACCESS64); return get_field(info->sbcs, DM_SBCS_SBACCESS64);
case 16: case 16:
return get_field(info->sbcs, DM_SBCS_SBACCESS128); return get_field(info->sbcs, DM_SBCS_SBACCESS128);
default: default:
return 0; return 0;
} }
} }
@@ -3113,19 +3113,19 @@ static void log_memory_access64(target_addr_t address, uint64_t value,
sprintf(fmt, "M[0x%" TARGET_PRIxADDR "] %ss 0x%%0%d" PRIx64, sprintf(fmt, "M[0x%" TARGET_PRIxADDR "] %ss 0x%%0%d" PRIx64,
address, is_read ? "read" : "write", size_bytes * 2); address, is_read ? "read" : "write", size_bytes * 2);
switch (size_bytes) { switch (size_bytes) {
case 1: case 1:
value &= 0xff; value &= 0xff;
break; break;
case 2: case 2:
value &= 0xffff; value &= 0xffff;
break; break;
case 4: case 4:
value &= 0xffffffffUL; value &= 0xffffffffUL;
break; break;
case 8: case 8:
break; break;
default: default:
assert(false); assert(false);
} }
LOG_DEBUG(fmt, value); LOG_DEBUG(fmt, value);
} }
@@ -4580,19 +4580,19 @@ riscv013_access_memory(struct target *target, const struct riscv_mem_access_args
for (unsigned int i = 0; i < r->num_enabled_mem_access_methods; ++i) { for (unsigned int i = 0; i < r->num_enabled_mem_access_methods; ++i) {
enum riscv_mem_access_method method = r->mem_access_methods[i]; enum riscv_mem_access_method method = r->mem_access_methods[i];
switch (method) { switch (method) {
case RISCV_MEM_ACCESS_PROGBUF: case RISCV_MEM_ACCESS_PROGBUF:
skip_reason[method] = access_memory_progbuf(target, args); skip_reason[method] = access_memory_progbuf(target, args);
break; break;
case RISCV_MEM_ACCESS_SYSBUS: case RISCV_MEM_ACCESS_SYSBUS:
skip_reason[method] = access_memory_sysbus(target, args); skip_reason[method] = access_memory_sysbus(target, args);
break; break;
case RISCV_MEM_ACCESS_ABSTRACT: case RISCV_MEM_ACCESS_ABSTRACT:
skip_reason[method] = access_memory_abstract(target, args); skip_reason[method] = access_memory_abstract(target, args);
break; break;
default: default:
LOG_TARGET_ERROR(target, "Unknown memory access method: %d", method); LOG_TARGET_ERROR(target, "Unknown memory access method: %d", method);
assert(false && "Unknown memory access method"); assert(false && "Unknown memory access method");
goto failure; goto failure;
} }
if (is_mem_access_failed(skip_reason[method])) if (is_mem_access_failed(skip_reason[method]))

594
src/target/riscv/riscv.c
View File

@@ -462,16 +462,16 @@ static struct target_type *get_target_type(struct target *target)
RISCV_INFO(info); RISCV_INFO(info);
switch (info->dtm_version) { switch (info->dtm_version) {
case DTM_DTMCS_VERSION_0_11: case DTM_DTMCS_VERSION_0_11:
return &riscv011_target; return &riscv011_target;
case DTM_DTMCS_VERSION_1_0: case DTM_DTMCS_VERSION_1_0:
return &riscv013_target; return &riscv013_target;
default: default:
/* TODO: once we have proper support for non-examined targets /* TODO: once we have proper support for non-examined targets
* we should have an assert here */ * we should have an assert here */
LOG_TARGET_ERROR(target, "Unsupported DTM version: %d", LOG_TARGET_ERROR(target, "Unsupported DTM version: %d",
info->dtm_version); info->dtm_version);
return NULL; return NULL;
} }
} }
@@ -1857,39 +1857,39 @@ static int riscv_trigger_detect_hit_bits(struct target *target, int64_t *unique_
uint64_t hit_mask = 0; uint64_t hit_mask = 0;
switch (type) { switch (type) {
case CSR_TDATA1_TYPE_LEGACY: case CSR_TDATA1_TYPE_LEGACY:
/* Doesn't support hit bit. */ /* Doesn't support hit bit. */
break; break;
case CSR_TDATA1_TYPE_MCONTROL: case CSR_TDATA1_TYPE_MCONTROL:
hit_mask = CSR_MCONTROL_HIT; hit_mask = CSR_MCONTROL_HIT;
*need_single_step = true;
break;
case CSR_TDATA1_TYPE_MCONTROL6:
hit_mask = CSR_MCONTROL6_HIT0 | CSR_MCONTROL6_HIT1;
if (r->tinfo_version == CSR_TINFO_VERSION_0) {
*need_single_step = true; *need_single_step = true;
break; } else if (r->tinfo_version == RISCV_TINFO_VERSION_UNKNOWN
case CSR_TDATA1_TYPE_MCONTROL6: || r->tinfo_version == CSR_TINFO_VERSION_1) {
hit_mask = CSR_MCONTROL6_HIT0 | CSR_MCONTROL6_HIT1; enum mctrl6hitstatus hits_status = check_mcontrol6_hit_status(target,
if (r->tinfo_version == CSR_TINFO_VERSION_0) { tdata1, hit_mask);
if (hits_status == M6_HIT_ERROR)
return ERROR_FAIL;
if (hits_status == M6_HIT_BEFORE || hits_status == M6_HIT_NOT_SUPPORTED)
*need_single_step = true; *need_single_step = true;
} else if (r->tinfo_version == RISCV_TINFO_VERSION_UNKNOWN }
|| r->tinfo_version == CSR_TINFO_VERSION_1) { break;
enum mctrl6hitstatus hits_status = check_mcontrol6_hit_status(target, case CSR_TDATA1_TYPE_ICOUNT:
tdata1, hit_mask); hit_mask = CSR_ICOUNT_HIT;
if (hits_status == M6_HIT_ERROR) break;
return ERROR_FAIL; case CSR_TDATA1_TYPE_ITRIGGER:
if (hits_status == M6_HIT_BEFORE || hits_status == M6_HIT_NOT_SUPPORTED) hit_mask = CSR_ITRIGGER_HIT(riscv_xlen(target));
*need_single_step = true; break;
} case CSR_TDATA1_TYPE_ETRIGGER:
break; hit_mask = CSR_ETRIGGER_HIT(riscv_xlen(target));
case CSR_TDATA1_TYPE_ICOUNT: break;
hit_mask = CSR_ICOUNT_HIT; default:
break; LOG_TARGET_DEBUG(target, "Trigger %u has unknown type %d", i, type);
case CSR_TDATA1_TYPE_ITRIGGER: continue;
hit_mask = CSR_ITRIGGER_HIT(riscv_xlen(target));
break;
case CSR_TDATA1_TYPE_ETRIGGER:
hit_mask = CSR_ETRIGGER_HIT(riscv_xlen(target));
break;
default:
LOG_TARGET_DEBUG(target, "Trigger %u has unknown type %d", i, type);
continue;
} }
/* FIXME: this logic needs to be changed to ignore triggers that are not /* FIXME: this logic needs to be changed to ignore triggers that are not
@@ -2562,71 +2562,71 @@ static int set_debug_reason(struct target *target, enum riscv_halt_reason halt_r
r->trigger_hit = -1; r->trigger_hit = -1;
r->need_single_step = false; r->need_single_step = false;
switch (halt_reason) { switch (halt_reason) {
case RISCV_HALT_EBREAK: case RISCV_HALT_EBREAK:
target->debug_reason = DBG_REASON_BREAKPOINT; target->debug_reason = DBG_REASON_BREAKPOINT;
break; break;
case RISCV_HALT_TRIGGER: case RISCV_HALT_TRIGGER:
target->debug_reason = DBG_REASON_UNDEFINED; target->debug_reason = DBG_REASON_UNDEFINED;
if (riscv_trigger_detect_hit_bits(target, &r->trigger_hit, if (riscv_trigger_detect_hit_bits(target, &r->trigger_hit,
&r->need_single_step) != ERROR_OK) &r->need_single_step) != ERROR_OK)
return ERROR_FAIL;
// FIXME: handle multiple hit bits
if (r->trigger_hit != RISCV_TRIGGER_HIT_NOT_FOUND) {
/* We scan for breakpoints first. If no breakpoints are found we still
* assume that debug reason is DBG_REASON_BREAKPOINT, unless
* there is a watchpoint match - This is to take
* ETrigger/ITrigger/ICount into account
*/
LOG_TARGET_DEBUG(target,
"Active hit bit is detected, trying to find trigger owner.");
for (struct breakpoint *bp = target->breakpoints; bp; bp = bp->next) {
if (bp->unique_id == r->trigger_hit) {
target->debug_reason = DBG_REASON_BREAKPOINT;
LOG_TARGET_DEBUG(target,
"Breakpoint with unique_id = %" PRIu32 " owns the trigger.",
bp->unique_id);
}
}
if (target->debug_reason == DBG_REASON_UNDEFINED) {
// by default we report all triggers as breakpoints
target->debug_reason = DBG_REASON_BREAKPOINT;
for (struct watchpoint *wp = target->watchpoints; wp; wp = wp->next) {
if (wp->unique_id == r->trigger_hit) {
target->debug_reason = DBG_REASON_WATCHPOINT;
LOG_TARGET_DEBUG(target,
"Watchpoint with unique_id = %" PRIu32 " owns the trigger.",
wp->unique_id);
}
}
}
} else {
LOG_TARGET_DEBUG(target,
"No trigger hit found, deriving debug reason without it.");
riscv_reg_t dpc;
if (riscv_reg_get(target, &dpc, GDB_REGNO_DPC) != ERROR_OK)
return ERROR_FAIL;
/* Here we don't have the hit bit set (likely, HW does not support it).
* We are trying to guess the state. But here comes the problem:
* if we have etrigger/itrigger/icount raised - we can't really
* distinguish it from the breakpoint or watchpoint. There is not
* much we can do here, except for checking current PC against pending
* breakpoints and hope for the best)
*/
target->debug_reason = derive_debug_reason_without_hitbit(target, dpc);
}
break;
case RISCV_HALT_INTERRUPT:
case RISCV_HALT_GROUP:
target->debug_reason = DBG_REASON_DBGRQ;
break;
case RISCV_HALT_SINGLESTEP:
target->debug_reason = DBG_REASON_SINGLESTEP;
break;
case RISCV_HALT_UNKNOWN:
target->debug_reason = DBG_REASON_UNDEFINED;
break;
case RISCV_HALT_ERROR:
return ERROR_FAIL; return ERROR_FAIL;
// FIXME: handle multiple hit bits
if (r->trigger_hit != RISCV_TRIGGER_HIT_NOT_FOUND) {
/* We scan for breakpoints first. If no breakpoints are found we still
* assume that debug reason is DBG_REASON_BREAKPOINT, unless
* there is a watchpoint match - This is to take
* ETrigger/ITrigger/ICount into account
*/
LOG_TARGET_DEBUG(target,
"Active hit bit is detected, trying to find trigger owner.");
for (struct breakpoint *bp = target->breakpoints; bp; bp = bp->next) {
if (bp->unique_id == r->trigger_hit) {
target->debug_reason = DBG_REASON_BREAKPOINT;
LOG_TARGET_DEBUG(target,
"Breakpoint with unique_id = %" PRIu32 " owns the trigger.",
bp->unique_id);
}
}
if (target->debug_reason == DBG_REASON_UNDEFINED) {
// by default we report all triggers as breakpoints
target->debug_reason = DBG_REASON_BREAKPOINT;
for (struct watchpoint *wp = target->watchpoints; wp; wp = wp->next) {
if (wp->unique_id == r->trigger_hit) {
target->debug_reason = DBG_REASON_WATCHPOINT;
LOG_TARGET_DEBUG(target,
"Watchpoint with unique_id = %" PRIu32 " owns the trigger.",
wp->unique_id);
}
}
}
} else {
LOG_TARGET_DEBUG(target,
"No trigger hit found, deriving debug reason without it.");
riscv_reg_t dpc;
if (riscv_reg_get(target, &dpc, GDB_REGNO_DPC) != ERROR_OK)
return ERROR_FAIL;
/* Here we don't have the hit bit set (likely, HW does not support it).
* We are trying to guess the state. But here comes the problem:
* if we have etrigger/itrigger/icount raised - we can't really
* distinguish it from the breakpoint or watchpoint. There is not
* much we can do here, except for checking current PC against pending
* breakpoints and hope for the best)
*/
target->debug_reason = derive_debug_reason_without_hitbit(target, dpc);
}
break;
case RISCV_HALT_INTERRUPT:
case RISCV_HALT_GROUP:
target->debug_reason = DBG_REASON_DBGRQ;
break;
case RISCV_HALT_SINGLESTEP:
target->debug_reason = DBG_REASON_SINGLESTEP;
break;
case RISCV_HALT_UNKNOWN:
target->debug_reason = DBG_REASON_UNDEFINED;
break;
case RISCV_HALT_ERROR:
return ERROR_FAIL;
} }
LOG_TARGET_DEBUG(target, "debug_reason=%d", target->debug_reason); LOG_TARGET_DEBUG(target, "debug_reason=%d", target->debug_reason);
@@ -3222,55 +3222,55 @@ static int riscv_virt2phys_v(struct target *target, target_addr_t virtual, targe
const virt2phys_info_t *vsatp_info; const virt2phys_info_t *vsatp_info;
/* VS-stage address translation. */ /* VS-stage address translation. */
switch (vsatp_mode) { switch (vsatp_mode) {
case SATP_MODE_SV32: case SATP_MODE_SV32:
vsatp_info = &sv32; vsatp_info = &sv32;
break; break;
case SATP_MODE_SV39: case SATP_MODE_SV39:
vsatp_info = &sv39; vsatp_info = &sv39;
break; break;
case SATP_MODE_SV48: case SATP_MODE_SV48:
vsatp_info = &sv48; vsatp_info = &sv48;
break; break;
case SATP_MODE_SV57: case SATP_MODE_SV57:
vsatp_info = &sv57; vsatp_info = &sv57;
break; break;
case SATP_MODE_OFF: case SATP_MODE_OFF:
vsatp_info = NULL; vsatp_info = NULL;
LOG_TARGET_DEBUG(target, "vsatp mode is %d. No VS-stage translation. (vsatp: 0x%" PRIx64 ")", LOG_TARGET_DEBUG(target, "vsatp mode is %d. No VS-stage translation. (vsatp: 0x%" PRIx64 ")",
vsatp_mode, vsatp); vsatp_mode, vsatp);
break; break;
default: default:
LOG_TARGET_ERROR(target, LOG_TARGET_ERROR(target,
"vsatp mode %d is not supported. (vsatp: 0x%" PRIx64 ")", "vsatp mode %d is not supported. (vsatp: 0x%" PRIx64 ")",
vsatp_mode, vsatp); vsatp_mode, vsatp);
return ERROR_FAIL; return ERROR_FAIL;
} }
const virt2phys_info_t *hgatp_info; const virt2phys_info_t *hgatp_info;
/* G-stage address translation. */ /* G-stage address translation. */
switch (hgatp_mode) { switch (hgatp_mode) {
case HGATP_MODE_SV32X4: case HGATP_MODE_SV32X4:
hgatp_info = &sv32x4; hgatp_info = &sv32x4;
break; break;
case HGATP_MODE_SV39X4: case HGATP_MODE_SV39X4:
hgatp_info = &sv39x4; hgatp_info = &sv39x4;
break; break;
case HGATP_MODE_SV48X4: case HGATP_MODE_SV48X4:
hgatp_info = &sv48x4; hgatp_info = &sv48x4;
break; break;
case HGATP_MODE_SV57X4: case HGATP_MODE_SV57X4:
hgatp_info = &sv57x4; hgatp_info = &sv57x4;
break; break;
case HGATP_MODE_OFF: case HGATP_MODE_OFF:
hgatp_info = NULL; hgatp_info = NULL;
LOG_TARGET_DEBUG(target, "hgatp mode is %d. No G-stage translation. (hgatp: 0x%" PRIx64 ")", LOG_TARGET_DEBUG(target, "hgatp mode is %d. No G-stage translation. (hgatp: 0x%" PRIx64 ")",
hgatp_mode, hgatp); hgatp_mode, hgatp);
break; break;
default: default:
LOG_TARGET_ERROR(target, LOG_TARGET_ERROR(target,
"hgatp mode %d is not supported. (hgatp: 0x%" PRIx64 ")", "hgatp mode %d is not supported. (hgatp: 0x%" PRIx64 ")",
hgatp_mode, hgatp); hgatp_mode, hgatp);
return ERROR_FAIL; return ERROR_FAIL;
} }
/* For any virtual memory access, the original virtual address is /* For any virtual memory access, the original virtual address is
@@ -3340,26 +3340,26 @@ static int riscv_virt2phys(struct target *target, target_addr_t virtual, target_
int satp_mode = get_field(satp_value, RISCV_SATP_MODE(xlen)); int satp_mode = get_field(satp_value, RISCV_SATP_MODE(xlen));
const virt2phys_info_t *satp_info; const virt2phys_info_t *satp_info;
switch (satp_mode) { switch (satp_mode) {
case SATP_MODE_SV32: case SATP_MODE_SV32:
satp_info = &sv32; satp_info = &sv32;
break; break;
case SATP_MODE_SV39: case SATP_MODE_SV39:
satp_info = &sv39; satp_info = &sv39;
break; break;
case SATP_MODE_SV48: case SATP_MODE_SV48:
satp_info = &sv48; satp_info = &sv48;
break; break;
case SATP_MODE_SV57: case SATP_MODE_SV57:
satp_info = &sv57; satp_info = &sv57;
break; break;
case SATP_MODE_OFF: case SATP_MODE_OFF:
LOG_TARGET_ERROR(target, "No translation or protection." LOG_TARGET_ERROR(target, "No translation or protection."
" (satp: 0x%" PRIx64 ")", satp_value); " (satp: 0x%" PRIx64 ")", satp_value);
return ERROR_FAIL; return ERROR_FAIL;
default: default:
LOG_TARGET_ERROR(target, "The translation mode is not supported." LOG_TARGET_ERROR(target, "The translation mode is not supported."
" (satp: 0x%" PRIx64 ")", satp_value); " (satp: 0x%" PRIx64 ")", satp_value);
return ERROR_FAIL; return ERROR_FAIL;
} }
return riscv_address_translate(target, return riscv_address_translate(target,
@@ -3503,10 +3503,10 @@ static int riscv_write_memory(struct target *target, target_addr_t address,
static const char *riscv_get_gdb_arch(const struct target *target) static const char *riscv_get_gdb_arch(const struct target *target)
{ {
switch (riscv_xlen(target)) { switch (riscv_xlen(target)) {
case 32: case 32:
return "riscv:rv32"; return "riscv:rv32";
case 64: case 64:
return "riscv:rv64"; return "riscv:rv64";
} }
LOG_TARGET_ERROR(target, "Unsupported xlen: %d", riscv_xlen(target)); LOG_TARGET_ERROR(target, "Unsupported xlen: %d", riscv_xlen(target));
return NULL; return NULL;
@@ -3524,15 +3524,15 @@ static int riscv_get_gdb_reg_list_internal(struct target *target,
} }
switch (reg_class) { switch (reg_class) {
case REG_CLASS_GENERAL: case REG_CLASS_GENERAL:
*reg_list_size = 33; *reg_list_size = 33;
break; break;
case REG_CLASS_ALL: case REG_CLASS_ALL:
*reg_list_size = target->reg_cache->num_regs; *reg_list_size = target->reg_cache->num_regs;
break; break;
default: default:
LOG_TARGET_ERROR(target, "Unsupported reg_class: %d", reg_class); LOG_TARGET_ERROR(target, "Unsupported reg_class: %d", reg_class);
return ERROR_FAIL; return ERROR_FAIL;
} }
*reg_list = calloc(*reg_list_size, sizeof(struct reg *)); *reg_list = calloc(*reg_list_size, sizeof(struct reg *));
@@ -3859,25 +3859,25 @@ static int riscv_poll_hart(struct target *target, enum riscv_next_action *next_a
enum riscv_hart_state previous_riscv_state = 0; enum riscv_hart_state previous_riscv_state = 0;
enum target_state previous_target_state = target->state; enum target_state previous_target_state = target->state;
switch (target->state) { switch (target->state) {
case TARGET_UNKNOWN: case TARGET_UNKNOWN:
/* Special case, handled further down. */ /* Special case, handled further down. */
previous_riscv_state = RISCV_STATE_UNAVAILABLE; /* Need to assign something. */ previous_riscv_state = RISCV_STATE_UNAVAILABLE; /* Need to assign something. */
break; break;
case TARGET_RUNNING: case TARGET_RUNNING:
previous_riscv_state = RISCV_STATE_RUNNING; previous_riscv_state = RISCV_STATE_RUNNING;
break; break;
case TARGET_HALTED: case TARGET_HALTED:
previous_riscv_state = RISCV_STATE_HALTED; previous_riscv_state = RISCV_STATE_HALTED;
break; break;
case TARGET_RESET: case TARGET_RESET:
previous_riscv_state = RISCV_STATE_HALTED; previous_riscv_state = RISCV_STATE_HALTED;
break; break;
case TARGET_DEBUG_RUNNING: case TARGET_DEBUG_RUNNING:
previous_riscv_state = RISCV_STATE_RUNNING; previous_riscv_state = RISCV_STATE_RUNNING;
break; break;
case TARGET_UNAVAILABLE: case TARGET_UNAVAILABLE:
previous_riscv_state = RISCV_STATE_UNAVAILABLE; previous_riscv_state = RISCV_STATE_UNAVAILABLE;
break; break;
} }
/* If OpenOCD thinks we're running but this hart is halted then it's time /* If OpenOCD thinks we're running but this hart is halted then it's time
@@ -3900,79 +3900,79 @@ static int riscv_poll_hart(struct target *target, enum riscv_next_action *next_a
if (target->state == TARGET_UNKNOWN || state != previous_riscv_state) { if (target->state == TARGET_UNKNOWN || state != previous_riscv_state) {
switch (state) { switch (state) {
case RISCV_STATE_HALTED: case RISCV_STATE_HALTED:
if (previous_riscv_state == RISCV_STATE_UNAVAILABLE) if (previous_riscv_state == RISCV_STATE_UNAVAILABLE)
LOG_TARGET_INFO(target, "became available (halted)"); LOG_TARGET_INFO(target, "became available (halted)");
LOG_TARGET_DEBUG(target, " triggered a halt; previous_target_state=%d", LOG_TARGET_DEBUG(target, " triggered a halt; previous_target_state=%d",
previous_target_state); previous_target_state);
target->state = TARGET_HALTED; target->state = TARGET_HALTED;
enum riscv_halt_reason halt_reason = riscv_halt_reason(target); enum riscv_halt_reason halt_reason = riscv_halt_reason(target);
if (set_debug_reason(target, halt_reason) != ERROR_OK) if (set_debug_reason(target, halt_reason) != ERROR_OK)
return ERROR_FAIL; return ERROR_FAIL;
if (halt_reason == RISCV_HALT_EBREAK) { if (halt_reason == RISCV_HALT_EBREAK) {
int retval; int retval;
/* Detect if this EBREAK is a semihosting request. If so, handle it. */ /* Detect if this EBREAK is a semihosting request. If so, handle it. */
switch (riscv_semihosting(target, &retval)) { switch (riscv_semihosting(target, &retval)) {
case SEMIHOSTING_NONE: case SEMIHOSTING_NONE:
break; break;
case SEMIHOSTING_WAITING: case SEMIHOSTING_WAITING:
/* This hart should remain halted. */ /* This hart should remain halted. */
*next_action = RPH_REMAIN_HALTED; *next_action = RPH_REMAIN_HALTED;
break; break;
case SEMIHOSTING_HANDLED: case SEMIHOSTING_HANDLED:
/* This hart should be resumed, along with any other /* This hart should be resumed, along with any other
* harts that halted due to haltgroups. */ * harts that halted due to haltgroups. */
*next_action = RPH_RESUME; *next_action = RPH_RESUME;
return ERROR_OK; return ERROR_OK;
case SEMIHOSTING_ERROR: case SEMIHOSTING_ERROR:
return retval; return retval;
}
} }
}
if (r->handle_became_halted && if (r->handle_became_halted &&
r->handle_became_halted(target, previous_riscv_state) != ERROR_OK) r->handle_became_halted(target, previous_riscv_state) != ERROR_OK)
return ERROR_FAIL; return ERROR_FAIL;
/* We shouldn't do the callbacks yet. What if /* We shouldn't do the callbacks yet. What if
* there are multiple harts that halted at the * there are multiple harts that halted at the
* same time? We need to set debug reason on each * same time? We need to set debug reason on each
* of them before calling a callback, which is * of them before calling a callback, which is
* going to figure out the "current thread". */ * going to figure out the "current thread". */
r->halted_needs_event_callback = true; r->halted_needs_event_callback = true;
if (previous_target_state == TARGET_DEBUG_RUNNING) if (previous_target_state == TARGET_DEBUG_RUNNING)
r->halted_callback_event = TARGET_EVENT_DEBUG_HALTED; r->halted_callback_event = TARGET_EVENT_DEBUG_HALTED;
else else
r->halted_callback_event = TARGET_EVENT_HALTED; r->halted_callback_event = TARGET_EVENT_HALTED;
break; break;
case RISCV_STATE_RUNNING: case RISCV_STATE_RUNNING:
if (previous_riscv_state == RISCV_STATE_UNAVAILABLE) if (previous_riscv_state == RISCV_STATE_UNAVAILABLE)
LOG_TARGET_INFO(target, "became available (running)"); LOG_TARGET_INFO(target, "became available (running)");
LOG_TARGET_DEBUG(target, " triggered running"); LOG_TARGET_DEBUG(target, " triggered running");
target->state = TARGET_RUNNING; target->state = TARGET_RUNNING;
target->debug_reason = DBG_REASON_NOTHALTED; target->debug_reason = DBG_REASON_NOTHALTED;
if (r->handle_became_running && if (r->handle_became_running &&
r->handle_became_running(target, previous_riscv_state) != ERROR_OK) r->handle_became_running(target, previous_riscv_state) != ERROR_OK)
return ERROR_FAIL; return ERROR_FAIL;
break; break;
case RISCV_STATE_UNAVAILABLE: case RISCV_STATE_UNAVAILABLE:
LOG_TARGET_DEBUG(target, " became unavailable"); LOG_TARGET_DEBUG(target, " became unavailable");
LOG_TARGET_INFO(target, "became unavailable."); LOG_TARGET_INFO(target, "became unavailable.");
target->state = TARGET_UNAVAILABLE; target->state = TARGET_UNAVAILABLE;
if (r->handle_became_unavailable && if (r->handle_became_unavailable &&
r->handle_became_unavailable(target, previous_riscv_state) != ERROR_OK) r->handle_became_unavailable(target, previous_riscv_state) != ERROR_OK)
return ERROR_FAIL; return ERROR_FAIL;
break; break;
case RISCV_STATE_NON_EXISTENT: case RISCV_STATE_NON_EXISTENT:
LOG_TARGET_ERROR(target, "Hart is non-existent!"); LOG_TARGET_ERROR(target, "Hart is non-existent!");
target->state = TARGET_UNAVAILABLE; target->state = TARGET_UNAVAILABLE;
break; break;
} }
} }
@@ -4072,19 +4072,19 @@ int riscv_openocd_poll(struct target *target)
return ERROR_FAIL; return ERROR_FAIL;
switch (next_action) { switch (next_action) {
case RPH_NONE: case RPH_NONE:
if (t->state == TARGET_HALTED) if (t->state == TARGET_HALTED)
halted++; halted++;
if (t->state == TARGET_RUNNING || if (t->state == TARGET_RUNNING ||
t->state == TARGET_DEBUG_RUNNING) t->state == TARGET_DEBUG_RUNNING)
running++; running++;
break; break;
case RPH_REMAIN_HALTED: case RPH_REMAIN_HALTED:
should_remain_halted++; should_remain_halted++;
break; break;
case RPH_RESUME: case RPH_RESUME:
should_resume++; should_resume++;
break; break;
} }
} }
@@ -6186,26 +6186,26 @@ static int disable_trigger_if_dmode(struct target *target, riscv_reg_t tdata1)
{ {
bool dmode_is_set = false; bool dmode_is_set = false;
switch (get_field(tdata1, CSR_TDATA1_TYPE(riscv_xlen(target)))) { switch (get_field(tdata1, CSR_TDATA1_TYPE(riscv_xlen(target)))) {
case CSR_TDATA1_TYPE_LEGACY: case CSR_TDATA1_TYPE_LEGACY:
/* On these older cores we don't support software using /* On these older cores we don't support software using
* triggers. */ * triggers. */
dmode_is_set = true; dmode_is_set = true;
break; break;
case CSR_TDATA1_TYPE_MCONTROL: case CSR_TDATA1_TYPE_MCONTROL:
dmode_is_set = tdata1 & CSR_MCONTROL_DMODE(riscv_xlen(target)); dmode_is_set = tdata1 & CSR_MCONTROL_DMODE(riscv_xlen(target));
break; break;
case CSR_TDATA1_TYPE_MCONTROL6: case CSR_TDATA1_TYPE_MCONTROL6:
dmode_is_set = tdata1 & CSR_MCONTROL6_DMODE(riscv_xlen(target)); dmode_is_set = tdata1 & CSR_MCONTROL6_DMODE(riscv_xlen(target));
break; break;
case CSR_TDATA1_TYPE_ICOUNT: case CSR_TDATA1_TYPE_ICOUNT:
dmode_is_set = tdata1 & CSR_ICOUNT_DMODE(riscv_xlen(target)); dmode_is_set = tdata1 & CSR_ICOUNT_DMODE(riscv_xlen(target));
break; break;
case CSR_TDATA1_TYPE_ITRIGGER: case CSR_TDATA1_TYPE_ITRIGGER:
dmode_is_set = tdata1 & CSR_ITRIGGER_DMODE(riscv_xlen(target)); dmode_is_set = tdata1 & CSR_ITRIGGER_DMODE(riscv_xlen(target));
break; break;
case CSR_TDATA1_TYPE_ETRIGGER: case CSR_TDATA1_TYPE_ETRIGGER:
dmode_is_set = tdata1 & CSR_ETRIGGER_DMODE(riscv_xlen(target)); dmode_is_set = tdata1 & CSR_ETRIGGER_DMODE(riscv_xlen(target));
break; break;
} }
if (!dmode_is_set) if (!dmode_is_set)
/* Nothing to do */ /* Nothing to do */

312
src/target/riscv/riscv_reg.c
View File

@@ -325,17 +325,17 @@ uint32_t gdb_regno_size(const struct target *target, uint32_t regno)
if (regno >= GDB_REGNO_CSR0 && regno <= GDB_REGNO_CSR4095) { if (regno >= GDB_REGNO_CSR0 && regno <= GDB_REGNO_CSR4095) {
const unsigned int csr_number = regno - GDB_REGNO_CSR0; const unsigned int csr_number = regno - GDB_REGNO_CSR0;
switch (csr_number) { switch (csr_number) {
case CSR_DCSR: case CSR_DCSR:
case CSR_MVENDORID: case CSR_MVENDORID:
case CSR_MCOUNTINHIBIT: case CSR_MCOUNTINHIBIT:
case CSR_FFLAGS: case CSR_FFLAGS:
case CSR_FRM: case CSR_FRM:
case CSR_FCSR: case CSR_FCSR:
case CSR_SCOUNTEREN: case CSR_SCOUNTEREN:
case CSR_MCOUNTEREN: case CSR_MCOUNTEREN:
return 32; return 32;
} }
} }
return riscv_xlen(target); return riscv_xlen(target);
@@ -393,154 +393,154 @@ bool riscv_reg_impl_gdb_regno_exist(const struct target *target, uint32_t regno)
assert(regno >= GDB_REGNO_CSR0 && regno <= GDB_REGNO_CSR4095); assert(regno >= GDB_REGNO_CSR0 && regno <= GDB_REGNO_CSR4095);
const unsigned int csr_number = regno - GDB_REGNO_CSR0; const unsigned int csr_number = regno - GDB_REGNO_CSR0;
switch (csr_number) { switch (csr_number) {
case CSR_FFLAGS: case CSR_FFLAGS:
case CSR_FRM: case CSR_FRM:
case CSR_FCSR: case CSR_FCSR:
return riscv_supports_extension(target, 'F'); return riscv_supports_extension(target, 'F');
case CSR_VSTART: case CSR_VSTART:
case CSR_VXSAT: case CSR_VXSAT:
case CSR_VXRM: case CSR_VXRM:
case CSR_VL: case CSR_VL:
case CSR_VCSR: case CSR_VCSR:
case CSR_VTYPE: case CSR_VTYPE:
return vlenb_exists(target); return vlenb_exists(target);
case CSR_SCOUNTEREN: case CSR_SCOUNTEREN:
case CSR_SSTATUS: case CSR_SSTATUS:
case CSR_STVEC: case CSR_STVEC:
case CSR_SIP: case CSR_SIP:
case CSR_SIE: case CSR_SIE:
case CSR_SSCRATCH: case CSR_SSCRATCH:
case CSR_SEPC: case CSR_SEPC:
case CSR_SCAUSE: case CSR_SCAUSE:
case CSR_STVAL: case CSR_STVAL:
case CSR_SATP: case CSR_SATP:
return riscv_supports_extension(target, 'S'); return riscv_supports_extension(target, 'S');
case CSR_MEDELEG: case CSR_MEDELEG:
case CSR_MIDELEG: case CSR_MIDELEG:
/* "In systems with only M-mode, or with both M-mode and /* "In systems with only M-mode, or with both M-mode and
* U-mode but without U-mode trap support, the medeleg and * U-mode but without U-mode trap support, the medeleg and
* mideleg registers should not exist." */ * mideleg registers should not exist." */
return riscv_supports_extension(target, 'S') || return riscv_supports_extension(target, 'S') ||
riscv_supports_extension(target, 'N'); riscv_supports_extension(target, 'N');
case CSR_PMPCFG1: case CSR_PMPCFG1:
case CSR_PMPCFG3: case CSR_PMPCFG3:
case CSR_CYCLEH: case CSR_CYCLEH:
case CSR_TIMEH: case CSR_TIMEH:
case CSR_INSTRETH: case CSR_INSTRETH:
case CSR_HPMCOUNTER3H: case CSR_HPMCOUNTER3H:
case CSR_HPMCOUNTER4H: case CSR_HPMCOUNTER4H:
case CSR_HPMCOUNTER5H: case CSR_HPMCOUNTER5H:
case CSR_HPMCOUNTER6H: case CSR_HPMCOUNTER6H:
case CSR_HPMCOUNTER7H: case CSR_HPMCOUNTER7H:
case CSR_HPMCOUNTER8H: case CSR_HPMCOUNTER8H:
case CSR_HPMCOUNTER9H: case CSR_HPMCOUNTER9H:
case CSR_HPMCOUNTER10H: case CSR_HPMCOUNTER10H:
case CSR_HPMCOUNTER11H: case CSR_HPMCOUNTER11H:
case CSR_HPMCOUNTER12H: case CSR_HPMCOUNTER12H:
case CSR_HPMCOUNTER13H: case CSR_HPMCOUNTER13H:
case CSR_HPMCOUNTER14H: case CSR_HPMCOUNTER14H:
case CSR_HPMCOUNTER15H: case CSR_HPMCOUNTER15H:
case CSR_HPMCOUNTER16H: case CSR_HPMCOUNTER16H:
case CSR_HPMCOUNTER17H: case CSR_HPMCOUNTER17H:
case CSR_HPMCOUNTER18H: case CSR_HPMCOUNTER18H:
case CSR_HPMCOUNTER19H: case CSR_HPMCOUNTER19H:
case CSR_HPMCOUNTER20H: case CSR_HPMCOUNTER20H:
case CSR_HPMCOUNTER21H: case CSR_HPMCOUNTER21H:
case CSR_HPMCOUNTER22H: case CSR_HPMCOUNTER22H:
case CSR_HPMCOUNTER23H: case CSR_HPMCOUNTER23H:
case CSR_HPMCOUNTER24H: case CSR_HPMCOUNTER24H:
case CSR_HPMCOUNTER25H: case CSR_HPMCOUNTER25H:
case CSR_HPMCOUNTER26H: case CSR_HPMCOUNTER26H:
case CSR_HPMCOUNTER27H: case CSR_HPMCOUNTER27H:
case CSR_HPMCOUNTER28H: case CSR_HPMCOUNTER28H:
case CSR_HPMCOUNTER29H: case CSR_HPMCOUNTER29H:
case CSR_HPMCOUNTER30H: case CSR_HPMCOUNTER30H:
case CSR_HPMCOUNTER31H: case CSR_HPMCOUNTER31H:
case CSR_MCYCLEH: case CSR_MCYCLEH:
case CSR_MINSTRETH: case CSR_MINSTRETH:
case CSR_MHPMCOUNTER4H: case CSR_MHPMCOUNTER4H:
case CSR_MHPMCOUNTER5H: case CSR_MHPMCOUNTER5H:
case CSR_MHPMCOUNTER6H: case CSR_MHPMCOUNTER6H:
case CSR_MHPMCOUNTER7H: case CSR_MHPMCOUNTER7H:
case CSR_MHPMCOUNTER8H: case CSR_MHPMCOUNTER8H:
case CSR_MHPMCOUNTER9H: case CSR_MHPMCOUNTER9H:
case CSR_MHPMCOUNTER10H: case CSR_MHPMCOUNTER10H:
case CSR_MHPMCOUNTER11H: case CSR_MHPMCOUNTER11H:
case CSR_MHPMCOUNTER12H: case CSR_MHPMCOUNTER12H:
case CSR_MHPMCOUNTER13H: case CSR_MHPMCOUNTER13H:
case CSR_MHPMCOUNTER14H: case CSR_MHPMCOUNTER14H:
case CSR_MHPMCOUNTER15H: case CSR_MHPMCOUNTER15H:
case CSR_MHPMCOUNTER16H: case CSR_MHPMCOUNTER16H:
case CSR_MHPMCOUNTER17H: case CSR_MHPMCOUNTER17H:
case CSR_MHPMCOUNTER18H: case CSR_MHPMCOUNTER18H:
case CSR_MHPMCOUNTER19H: case CSR_MHPMCOUNTER19H:
case CSR_MHPMCOUNTER20H: case CSR_MHPMCOUNTER20H:
case CSR_MHPMCOUNTER21H: case CSR_MHPMCOUNTER21H:
case CSR_MHPMCOUNTER22H: case CSR_MHPMCOUNTER22H:
case CSR_MHPMCOUNTER23H: case CSR_MHPMCOUNTER23H:
case CSR_MHPMCOUNTER24H: case CSR_MHPMCOUNTER24H:
case CSR_MHPMCOUNTER25H: case CSR_MHPMCOUNTER25H:
case CSR_MHPMCOUNTER26H: case CSR_MHPMCOUNTER26H:
case CSR_MHPMCOUNTER27H: case CSR_MHPMCOUNTER27H:
case CSR_MHPMCOUNTER28H: case CSR_MHPMCOUNTER28H:
case CSR_MHPMCOUNTER29H: case CSR_MHPMCOUNTER29H:
case CSR_MHPMCOUNTER30H: case CSR_MHPMCOUNTER30H:
case CSR_MHPMCOUNTER31H: case CSR_MHPMCOUNTER31H:
return riscv_xlen(target) == 32; return riscv_xlen(target) == 32;
case CSR_MCOUNTEREN: case CSR_MCOUNTEREN:
return riscv_supports_extension(target, 'U'); return riscv_supports_extension(target, 'U');
/* Interrupts M-Mode CSRs. */ /* Interrupts M-Mode CSRs. */
case CSR_MISELECT: case CSR_MISELECT:
case CSR_MIREG: case CSR_MIREG:
case CSR_MVIEN: case CSR_MVIEN:
case CSR_MVIP: case CSR_MVIP:
case CSR_MIEH: case CSR_MIEH:
case CSR_MIPH: case CSR_MIPH:
return reg_exists(target, GDB_REGNO_MTOPI); return reg_exists(target, GDB_REGNO_MTOPI);
case CSR_MIDELEGH: case CSR_MIDELEGH:
case CSR_MVIENH: case CSR_MVIENH:
case CSR_MVIPH: case CSR_MVIPH:
return reg_exists(target, GDB_REGNO_MTOPI) && return reg_exists(target, GDB_REGNO_MTOPI) &&
riscv_xlen(target) == 32 && riscv_xlen(target) == 32 &&
riscv_supports_extension(target, 'S'); riscv_supports_extension(target, 'S');
/* Interrupts S-Mode CSRs. */ /* Interrupts S-Mode CSRs. */
case CSR_SISELECT: case CSR_SISELECT:
case CSR_SIREG: case CSR_SIREG:
case CSR_STOPI: case CSR_STOPI:
return reg_exists(target, GDB_REGNO_MTOPI) && return reg_exists(target, GDB_REGNO_MTOPI) &&
riscv_supports_extension(target, 'S'); riscv_supports_extension(target, 'S');
case CSR_STOPEI: case CSR_STOPEI:
return reg_exists(target, GDB_REGNO_MTOPEI) && return reg_exists(target, GDB_REGNO_MTOPEI) &&
riscv_supports_extension(target, 'S'); riscv_supports_extension(target, 'S');
case CSR_SIEH: case CSR_SIEH:
case CSR_SIPH: case CSR_SIPH:
return reg_exists(target, GDB_REGNO_MTOPI) && return reg_exists(target, GDB_REGNO_MTOPI) &&
riscv_xlen(target) == 32 && riscv_xlen(target) == 32 &&
riscv_supports_extension(target, 'S'); riscv_supports_extension(target, 'S');
/* Interrupts Hypervisor and VS CSRs. */ /* Interrupts Hypervisor and VS CSRs. */
case CSR_HVIEN: case CSR_HVIEN:
case CSR_HVICTL: case CSR_HVICTL:
case CSR_HVIPRIO1: case CSR_HVIPRIO1:
case CSR_HVIPRIO2: case CSR_HVIPRIO2:
case CSR_VSISELECT: case CSR_VSISELECT:
case CSR_VSIREG: case CSR_VSIREG:
case CSR_VSTOPI: case CSR_VSTOPI:
return reg_exists(target, GDB_REGNO_MTOPI) && return reg_exists(target, GDB_REGNO_MTOPI) &&
riscv_supports_extension(target, 'H'); riscv_supports_extension(target, 'H');
case CSR_VSTOPEI: case CSR_VSTOPEI:
return reg_exists(target, GDB_REGNO_MTOPEI) && return reg_exists(target, GDB_REGNO_MTOPEI) &&
riscv_supports_extension(target, 'H'); riscv_supports_extension(target, 'H');
case CSR_HIDELEGH: case CSR_HIDELEGH:
case CSR_HVIENH: case CSR_HVIENH:
case CSR_HVIPH: case CSR_HVIPH:
case CSR_HVIPRIO1H: case CSR_HVIPRIO1H:
case CSR_HVIPRIO2H: case CSR_HVIPRIO2H:
case CSR_VSIEH: case CSR_VSIEH:
case CSR_VSIPH: case CSR_VSIPH:
return reg_exists(target, GDB_REGNO_MTOPI) && return reg_exists(target, GDB_REGNO_MTOPI) &&
riscv_xlen(target) == 32 && riscv_xlen(target) == 32 &&
riscv_supports_extension(target, 'H'); riscv_supports_extension(target, 'H');
} }
return is_known_standard_csr(csr_number); return is_known_standard_csr(csr_number);
} }

44
src/target/riscv/riscv_reg_impl.h
View File

@@ -194,29 +194,29 @@ static inline bool riscv_reg_impl_gdb_regno_cacheable(enum gdb_regno regno,
/* Most CSRs won't change value on us, but we can't assume it about arbitrary /* Most CSRs won't change value on us, but we can't assume it about arbitrary
* CSRs. */ * CSRs. */
switch (regno) { switch (regno) {
case GDB_REGNO_DPC: case GDB_REGNO_DPC:
case GDB_REGNO_VSTART: case GDB_REGNO_VSTART:
case GDB_REGNO_VXSAT: case GDB_REGNO_VXSAT:
case GDB_REGNO_VXRM: case GDB_REGNO_VXRM:
case GDB_REGNO_VLENB: case GDB_REGNO_VLENB:
case GDB_REGNO_VL: case GDB_REGNO_VL:
case GDB_REGNO_VTYPE: case GDB_REGNO_VTYPE:
case GDB_REGNO_MISA: case GDB_REGNO_MISA:
case GDB_REGNO_DCSR: case GDB_REGNO_DCSR:
case GDB_REGNO_DSCRATCH0: case GDB_REGNO_DSCRATCH0:
case GDB_REGNO_MEPC: case GDB_REGNO_MEPC:
case GDB_REGNO_SATP: case GDB_REGNO_SATP:
/* /*
* WARL registers might not contain the value we just wrote, but * WARL registers might not contain the value we just wrote, but
* these ones won't spontaneously change their value either. * * these ones won't spontaneously change their value either. *
*/ */
return !is_write; return !is_write;
case GDB_REGNO_TSELECT: /* I think this should be above, but then it doesn't work. */ case GDB_REGNO_TSELECT: /* I think this should be above, but then it doesn't work. */
case GDB_REGNO_TDATA1: /* Changes value when tselect is changed. */ case GDB_REGNO_TDATA1: /* Changes value when tselect is changed. */
case GDB_REGNO_TDATA2: /* Changes value when tselect is changed. */ case GDB_REGNO_TDATA2: /* Changes value when tselect is changed. */
default: default:
return false; return false;
} }
} }
#endif /* OPENOCD_TARGET_RISCV_RISCV_REG_IMPL_H */ #endif /* OPENOCD_TARGET_RISCV_RISCV_REG_IMPL_H */