auracaster/sw_openocd
3
0
Fork 0
forked from auracaster/openocd
Code Pull Requests Activity

target/espressif: add semihosting support

Browse Source 
ARM semihosting + some custom syscalls implemented for
Espressif chips (ESP32, ESP32-S2, ESP32-S3)

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Ic8174cf1cd344fa16d619b7b8405c9650e869443
Reviewed-on: https://review.openocd.org/c/openocd/+/7074
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Erhan Kurubas
2022-06-30 13:14:27 +03:00
committed by Antonio Borneo
parent 7dc4be3157
commit bea4d65903
16 changed files with 510 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
src/target/espressif/esp_xtensa_semihosting.h Normal file
View File

@@ -0,0 +1,15 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/***************************************************************************
* Copyright (c) 2020 Espressif Systems (Shanghai) Co. Ltd. *
***************************************************************************/
#ifndef OPENOCD_TARGET_ESP_XTENSA_SEMIHOSTING_H
#define OPENOCD_TARGET_ESP_XTENSA_SEMIHOSTING_H
#include <target/target.h>
int esp_xtensa_semihosting_init(struct target *target);
int esp_xtensa_semihosting(struct target *target, int *retval);
#endif /* OPENOCD_TARGET_ESP_XTENSA_SEMIHOSTING_H */