auracaster/sw_openocd
3
0
Fork 0
forked from auracaster/openocd
Code Pull Requests Activity

flash/nor: use target_addr_t for flash bank base

Browse Source 
This should allow users to configure flash at >32-bit addresses.

Change-Id: I7c9d3c5762579011a2d9708e5317e5765349845c
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/4919
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit is contained in:
Tim Newsome
2019-02-14 17:33:28 -08:00
committed by Matthias Welwarsky
parent 57e30102ea
commit c3b90c052a
28 changed files with 121 additions and 98 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
src/flash/nor/tms470.c
View File

@@ -165,7 +165,8 @@ static int tms470_read_part_info(struct flash_bank *bank)
part_name = "TMS470R1A256";
if (bank->base >= 0x00040000) {
LOG_ERROR("No %s flash bank contains base address 0x%08" PRIx32 ".",
LOG_ERROR("No %s flash bank contains base address "
TARGET_ADDR_FMT ".",
part_name,
bank->base);
return ERROR_FLASH_OPERATION_FAILED;
@@ -204,7 +205,7 @@ static int tms470_read_part_info(struct flash_bank *bank)
(void)memcpy(bank->sectors, TMS470R1A288_BANK1_SECTORS,
sizeof(TMS470R1A288_BANK1_SECTORS));
} else {
LOG_ERROR("No %s flash bank contains base address 0x%08" PRIx32 ".",
LOG_ERROR("No %s flash bank contains base address " TARGET_ADDR_FMT ".",
part_name, bank->base);
return ERROR_FLASH_OPERATION_FAILED;
}
@@ -244,7 +245,7 @@ static int tms470_read_part_info(struct flash_bank *bank)
(void)memcpy(bank->sectors, TMS470R1A384_BANK2_SECTORS,
sizeof(TMS470R1A384_BANK2_SECTORS));
} else {
LOG_ERROR("No %s flash bank contains base address 0x%08" PRIx32 ".",
LOG_ERROR("No %s flash bank contains base address " TARGET_ADDR_FMT ".",
part_name, bank->base);
return ERROR_FLASH_OPERATION_FAILED;
}
@@ -900,8 +901,8 @@ static int tms470_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t
tms470_read_part_info(bank);
LOG_INFO("Writing %" PRId32 " bytes starting at 0x%08" PRIx32 "", count, bank->base +
offset);
LOG_INFO("Writing %" PRId32 " bytes starting at " TARGET_ADDR_FMT,
count, bank->base + offset);
/* set GLBCTRL.4 */
target_read_u32(target, 0xFFFFFFDC, &glbctrl);