forked from auracaster/openocd
nds32: add new target type nds32_v2, nds32_v3, nds32_v3m
Add target code for Andes targets. Change-Id: Ibf0e1b61b06127ca7d9ed502d98d7e2aeebbbe82 Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com> Reviewed-on: http://openocd.zylin.com/1259 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This commit is contained in:
Hsiangkai Wang
committed by
Spencer Oliver
Spencer Oliver
parent
ceb402dc9e
commit
cf8a3c3d70
492
src/target/nds32_v3_common.c
Normal file
492
src/target/nds32_v3_common.c
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@@ -0,0 +1,492 @@
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/***************************************************************************
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* Copyright (C) 2013 Andes Technology *
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* Hsiangkai Wang <hkwang@andestech.com> *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "breakpoints.h"
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#include "nds32_reg.h"
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#include "nds32_disassembler.h"
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#include "nds32.h"
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#include "nds32_aice.h"
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#include "nds32_v3_common.h"
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static struct nds32_v3_common_callback *v3_common_callback;
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static int nds32_v3_register_mapping(struct nds32 *nds32, int reg_no)
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{
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if (reg_no == PC)
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return IR11;
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return reg_no;
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}
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static int nds32_v3_get_debug_reason(struct nds32 *nds32, uint32_t *reason)
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{
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uint32_t edmsw;
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struct aice_port_s *aice = target_to_aice(nds32->target);
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aice_read_debug_reg(aice, NDS_EDM_SR_EDMSW, &edmsw);
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*reason = (edmsw >> 12) & 0x0F;
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return ERROR_OK;
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}
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/**
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* Save processor state. This is called after a HALT instruction
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* succeeds, and on other occasions the processor enters debug mode
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* (breakpoint, watchpoint, etc).
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*/
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static int nds32_v3_debug_entry(struct nds32 *nds32, bool enable_watchpoint)
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{
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LOG_DEBUG("nds32_v3_debug_entry");
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jtag_poll_set_enabled(false);
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enum target_state backup_state = nds32->target->state;
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nds32->target->state = TARGET_HALTED;
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if (nds32->init_arch_info_after_halted == false) {
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/* init architecture info according to config registers */
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CHECK_RETVAL(nds32_config(nds32));
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nds32->init_arch_info_after_halted = true;
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}
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/* REVISIT entire cache should already be invalid !!! */
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register_cache_invalidate(nds32->core_cache);
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/* deactivate all hardware breakpoints */
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CHECK_RETVAL(v3_common_callback->deactivate_hardware_breakpoint(nds32->target));
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if (enable_watchpoint)
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CHECK_RETVAL(v3_common_callback->deactivate_hardware_watchpoint(nds32->target));
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if (ERROR_OK != nds32_examine_debug_reason(nds32)) {
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nds32->target->state = backup_state;
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/* re-activate all hardware breakpoints & watchpoints */
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CHECK_RETVAL(v3_common_callback->activate_hardware_breakpoint(nds32->target));
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if (enable_watchpoint)
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CHECK_RETVAL(v3_common_callback->activate_hardware_watchpoint(nds32->target));
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jtag_poll_set_enabled(true);
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return ERROR_FAIL;
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}
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/* Save registers. */
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nds32_full_context(nds32);
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/* check interrupt level */
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v3_common_callback->check_interrupt_stack(nds32);
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return ERROR_OK;
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}
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/**
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* Restore processor state.
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*/
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static int nds32_v3_leave_debug_state(struct nds32 *nds32, bool enable_watchpoint)
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{
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LOG_DEBUG("nds32_v3_leave_debug_state");
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struct target *target = nds32->target;
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/* activate all hardware breakpoints */
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CHECK_RETVAL(v3_common_callback->activate_hardware_breakpoint(target));
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if (enable_watchpoint) {
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/* activate all watchpoints */
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CHECK_RETVAL(v3_common_callback->activate_hardware_watchpoint(target));
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}
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/* restore interrupt stack */
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v3_common_callback->restore_interrupt_stack(nds32);
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/* REVISIT once we start caring about MMU and cache state,
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* address it here ...
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*/
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/* restore PSW, PC, and R0 ... after flushing any modified
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* registers.
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*/
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CHECK_RETVAL(nds32_restore_context(target));
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/* enable polling */
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jtag_poll_set_enabled(true);
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return ERROR_OK;
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}
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static int nds32_v3_get_exception_address(struct nds32 *nds32,
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uint32_t *address, uint32_t reason)
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{
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LOG_DEBUG("nds32_v3_get_exception_address");
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struct aice_port_s *aice = target_to_aice(nds32->target);
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struct target *target = nds32->target;
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uint32_t edmsw;
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uint32_t edm_cfg;
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uint32_t match_bits;
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uint32_t match_count;
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int32_t i;
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static int32_t number_of_hard_break;
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if (number_of_hard_break == 0) {
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aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CFG, &edm_cfg);
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number_of_hard_break = (edm_cfg & 0x7) + 1;
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}
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aice_read_debug_reg(aice, NDS_EDM_SR_EDMSW, &edmsw);
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/* clear matching bits (write-one-clear) */
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aice_write_debug_reg(aice, NDS_EDM_SR_EDMSW, edmsw);
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match_bits = (edmsw >> 4) & 0xFF;
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match_count = 0;
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for (i = 0 ; i < number_of_hard_break ; i++) {
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if (match_bits & (1 << i)) {
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aice_read_debug_reg(aice, NDS_EDM_SR_BPA0 + i, address);
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match_count++;
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}
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}
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if (match_count > 1) { /* multiple hits */
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*address = 0;
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return ERROR_OK;
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} else if (match_count == 1) {
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uint32_t val_pc;
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uint32_t opcode;
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struct nds32_instruction instruction;
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struct watchpoint *wp;
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bool hit;
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nds32_get_mapped_reg(nds32, PC, &val_pc);
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if ((NDS32_DEBUG_DATA_ADDR_WATCHPOINT_NEXT_PRECISE == reason) ||
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(NDS32_DEBUG_DATA_VALUE_WATCHPOINT_NEXT_PRECISE == reason)) {
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if (edmsw & 0x4) /* check EDMSW.IS_16BIT */
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val_pc -= 2;
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else
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val_pc -= 4;
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}
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nds32_read_opcode(nds32, val_pc, &opcode);
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nds32_evaluate_opcode(nds32, opcode, val_pc, &instruction);
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LOG_DEBUG("PC: 0x%08x, access start: 0x%08x, end: 0x%08x", val_pc,
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instruction.access_start, instruction.access_end);
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/* check if multiple hits in the access range */
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uint32_t in_range_watch_count = 0;
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for (wp = target->watchpoints; wp; wp = wp->next) {
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if ((instruction.access_start <= wp->address) &&
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(wp->address < instruction.access_end))
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in_range_watch_count++;
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}
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if (in_range_watch_count > 1) {
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/* Hit LSMW instruction. */
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*address = 0;
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return ERROR_OK;
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}
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/* dispel false match */
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hit = false;
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for (wp = target->watchpoints; wp; wp = wp->next) {
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if (((*address ^ wp->address) & (~wp->mask)) == 0) {
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uint32_t watch_start;
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uint32_t watch_end;
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watch_start = wp->address;
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watch_end = wp->address + wp->length;
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if ((watch_end <= instruction.access_start) ||
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(instruction.access_end <= watch_start))
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continue;
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hit = true;
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break;
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}
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}
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if (hit)
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return ERROR_OK;
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else
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return ERROR_FAIL;
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} else if (match_count == 0) {
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/* global stop is precise exception */
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if ((NDS32_DEBUG_LOAD_STORE_GLOBAL_STOP == reason) && nds32->global_stop) {
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/* parse instruction to get correct access address */
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uint32_t val_pc;
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uint32_t opcode;
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struct nds32_instruction instruction;
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nds32_get_mapped_reg(nds32, PC, &val_pc);
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nds32_read_opcode(nds32, val_pc, &opcode);
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nds32_evaluate_opcode(nds32, opcode, val_pc, &instruction);
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*address = instruction.access_start;
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return ERROR_OK;
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}
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}
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*address = 0xFFFFFFFF;
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return ERROR_FAIL;
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}
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void nds32_v3_common_register_callback(struct nds32_v3_common_callback *callback)
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{
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v3_common_callback = callback;
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}
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/** target_type functions: */
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/* target request support */
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int nds32_v3_target_request_data(struct target *target,
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uint32_t size, uint8_t *buffer)
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{
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/* AndesCore could use DTR register to communicate with OpenOCD
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* to output messages
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* Target data will be put in buffer
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* The format of DTR is as follow
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* DTR[31:16] => length, DTR[15:8] => size, DTR[7:0] => target_req_cmd
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* target_req_cmd has three possible values:
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* TARGET_REQ_TRACEMSG
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* TARGET_REQ_DEBUGMSG
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* TARGET_REQ_DEBUGCHAR
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* if size == 0, target will call target_asciimsg(),
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* else call target_hexmsg()
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*/
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LOG_WARNING("Not implemented: %s", __func__);
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return ERROR_OK;
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}
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int nds32_v3_soft_reset_halt(struct target *target)
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{
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struct aice_port_s *aice = target_to_aice(target);
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return aice_assert_srst(aice, AICE_RESET_HOLD);
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}
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int nds32_v3_checksum_memory(struct target *target,
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uint32_t address, uint32_t count, uint32_t *checksum)
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{
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LOG_WARNING("Not implemented: %s", __func__);
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return ERROR_FAIL;
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}
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int nds32_v3_target_create_common(struct target *target, struct nds32 *nds32)
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{
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nds32->register_map = nds32_v3_register_mapping;
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nds32->get_debug_reason = nds32_v3_get_debug_reason;
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nds32->enter_debug_state = nds32_v3_debug_entry;
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nds32->leave_debug_state = nds32_v3_leave_debug_state;
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nds32->get_watched_address = nds32_v3_get_exception_address;
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/* Init target->arch_info in nds32_init_arch_info().
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* After this, user could use target_to_nds32() to get nds32 object */
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nds32_init_arch_info(target, nds32);
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return ERROR_OK;
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}
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int nds32_v3_run_algorithm(struct target *target,
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int num_mem_params,
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struct mem_param *mem_params,
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int num_reg_params,
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struct reg_param *reg_params,
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uint32_t entry_point,
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uint32_t exit_point,
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int timeout_ms,
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void *arch_info)
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{
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LOG_WARNING("Not implemented: %s", __func__);
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return ERROR_FAIL;
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}
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int nds32_v3_read_buffer(struct target *target, uint32_t address,
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uint32_t size, uint8_t *buffer)
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{
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struct nds32 *nds32 = target_to_nds32(target);
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struct nds32_memory *memory = &(nds32->memory);
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if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
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(target->state != TARGET_HALTED)) {
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LOG_WARNING("target was not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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uint32_t physical_address;
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/* BUG: If access range crosses multiple pages, the translation will not correct
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* for second page or so. */
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/* When DEX is set to one, hardware will enforce the following behavior without
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* modifying the corresponding control bits in PSW.
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*
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* Disable all interrupts
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* Become superuser mode
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* Turn off IT/DT
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* Use MMU_CFG.DE as the data access endian
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* Use MMU_CFG.DRDE as the device register access endian if MMU_CTL.DREE is asserted
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* Disable audio special features
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* Disable inline function call
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*
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* Because hardware will turn off IT/DT by default, it MUST translate virtual address
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* to physical address.
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*/
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if (ERROR_OK == target->type->virt2phys(target, address, &physical_address))
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address = physical_address;
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else
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return ERROR_FAIL;
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return nds32_read_buffer(target, address, size, buffer);
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}
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int nds32_v3_write_buffer(struct target *target, uint32_t address,
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uint32_t size, const uint8_t *buffer)
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{
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struct nds32 *nds32 = target_to_nds32(target);
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struct nds32_memory *memory = &(nds32->memory);
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if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
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(target->state != TARGET_HALTED)) {
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LOG_WARNING("target was not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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uint32_t physical_address;
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/* BUG: If access range crosses multiple pages, the translation will not correct
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* for second page or so. */
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/* When DEX is set to one, hardware will enforce the following behavior without
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* modifying the corresponding control bits in PSW.
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*
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* Disable all interrupts
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* Become superuser mode
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* Turn off IT/DT
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* Use MMU_CFG.DE as the data access endian
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* Use MMU_CFG.DRDE as the device register access endian if MMU_CTL.DREE is asserted
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* Disable audio special features
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* Disable inline function call
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*
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* Because hardware will turn off IT/DT by default, it MUST translate virtual address
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* to physical address.
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*/
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if (ERROR_OK == target->type->virt2phys(target, address, &physical_address))
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address = physical_address;
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else
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return ERROR_FAIL;
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return nds32_write_buffer(target, address, size, buffer);
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}
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int nds32_v3_read_memory(struct target *target, uint32_t address,
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uint32_t size, uint32_t count, uint8_t *buffer)
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{
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struct nds32 *nds32 = target_to_nds32(target);
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struct nds32_memory *memory = &(nds32->memory);
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if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
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(target->state != TARGET_HALTED)) {
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LOG_WARNING("target was not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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uint32_t physical_address;
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/* BUG: If access range crosses multiple pages, the translation will not correct
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* for second page or so. */
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/* When DEX is set to one, hardware will enforce the following behavior without
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* modifying the corresponding control bits in PSW.
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*
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* Disable all interrupts
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* Become superuser mode
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* Turn off IT/DT
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* Use MMU_CFG.DE as the data access endian
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* Use MMU_CFG.DRDE as the device register access endian if MMU_CTL.DREE is asserted
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* Disable audio special features
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* Disable inline function call
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*
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* Because hardware will turn off IT/DT by default, it MUST translate virtual address
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* to physical address.
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*/
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if (ERROR_OK == target->type->virt2phys(target, address, &physical_address))
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address = physical_address;
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else
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return ERROR_FAIL;
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int result;
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result = nds32_read_memory(target, address, size, count, buffer);
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return result;
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}
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int nds32_v3_write_memory(struct target *target, uint32_t address,
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uint32_t size, uint32_t count, const uint8_t *buffer)
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{
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struct nds32 *nds32 = target_to_nds32(target);
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struct nds32_memory *memory = &(nds32->memory);
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if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
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(target->state != TARGET_HALTED)) {
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LOG_WARNING("target was not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
|
||||
|
||||
uint32_t physical_address;
|
||||
/* BUG: If access range crosses multiple pages, the translation will not correct
|
||||
* for second page or so. */
|
||||
|
||||
/* When DEX is set to one, hardware will enforce the following behavior without
|
||||
* modifying the corresponding control bits in PSW.
|
||||
*
|
||||
* Disable all interrupts
|
||||
* Become superuser mode
|
||||
* Turn off IT/DT
|
||||
* Use MMU_CFG.DE as the data access endian
|
||||
* Use MMU_CFG.DRDE as the device register access endian if MMU_CTL.DREE is asserted
|
||||
* Disable audio special features
|
||||
* Disable inline function call
|
||||
*
|
||||
* Because hardware will turn off IT/DT by default, it MUST translate virtual address
|
||||
* to physical address.
|
||||
*/
|
||||
if (ERROR_OK == target->type->virt2phys(target, address, &physical_address))
|
||||
address = physical_address;
|
||||
else
|
||||
return ERROR_FAIL;
|
||||
|
||||
return nds32_write_memory(target, address, size, count, buffer);
|
||||
}
|
||||
|
||||
int nds32_v3_init_target(struct command_context *cmd_ctx,
|
||||
struct target *target)
|
||||
{
|
||||
/* Initialize anything we can set up without talking to the target */
|
||||
struct nds32 *nds32 = target_to_nds32(target);
|
||||
|
||||
nds32_init(nds32);
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
Reference in New Issue
Block a user