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arm_opcode: Add support for ARM MCRR/MRRC

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Add support for the ARM MCRR/MRRC instructions which require the use of
two registers to transfer a 64-bit co-processor registers. We are going
to use this in a subsequent patch in order to properly dump 64-bit page
table descriptors that exist on ARMv7A with VMSA extensions.

We make use of r0 and r1 to transfer 64-bit quantities to/from DCC.

Change-Id: Ic4975026c1ae4f2853795575ac7701d541248736
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Michael Chalfant <michael.chalfant@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/5228
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Florian Fainelli
2019-03-18 16:00:07 -07:00
committed by Antonio Borneo
parent 1bc4182ceb
commit d27a3a00b8
6 changed files with 262 additions and 0 deletions
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47
src/target/cortex_a.c
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@@ -471,6 +471,28 @@ static int cortex_a_instr_write_data_r0(struct arm_dpm *dpm,
return retval;
}
static int cortex_a_instr_write_data_r0_r1(struct arm_dpm *dpm,
uint32_t opcode, uint64_t data)
{
struct cortex_a_common *a = dpm_to_a(dpm);
uint32_t dscr = DSCR_INSTR_COMP;
int retval;
retval = cortex_a_instr_write_data_rt_dcc(dpm, 0, data & 0xffffffffULL);
if (retval != ERROR_OK)
return retval;
retval = cortex_a_instr_write_data_rt_dcc(dpm, 1, data >> 32);
if (retval != ERROR_OK)
return retval;
/* then the opcode, taking data from R0, R1 */
retval = cortex_a_exec_opcode(a->armv7a_common.arm.target,
opcode,
&dscr);
return retval;
}
static int cortex_a_instr_cpsr_sync(struct arm_dpm *dpm)
{
struct target *target = dpm->arm->target;
@@ -539,6 +561,29 @@ static int cortex_a_instr_read_data_r0(struct arm_dpm *dpm,
return cortex_a_instr_read_data_rt_dcc(dpm, 0, data);
}
static int cortex_a_instr_read_data_r0_r1(struct arm_dpm *dpm,
uint32_t opcode, uint64_t *data)
{
uint32_t lo, hi;
int retval;
/* the opcode, writing data to RO, R1 */
retval = cortex_a_instr_read_data_r0(dpm, opcode, &lo);
if (retval != ERROR_OK)
return retval;
*data = lo;
/* write R1 to DCC */
retval = cortex_a_instr_read_data_rt_dcc(dpm, 1, &hi);
if (retval != ERROR_OK)
return retval;
*data |= (uint64_t)hi << 32;
return retval;
}
static int cortex_a_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
uint32_t addr, uint32_t control)
{
@@ -612,10 +657,12 @@ static int cortex_a_dpm_setup(struct cortex_a_common *a, uint32_t didr)
dpm->instr_write_data_dcc = cortex_a_instr_write_data_dcc;
dpm->instr_write_data_r0 = cortex_a_instr_write_data_r0;
dpm->instr_write_data_r0_r1 = cortex_a_instr_write_data_r0_r1;
dpm->instr_cpsr_sync = cortex_a_instr_cpsr_sync;
dpm->instr_read_data_dcc = cortex_a_instr_read_data_dcc;
dpm->instr_read_data_r0 = cortex_a_instr_read_data_r0;
dpm->instr_read_data_r0_r1 = cortex_a_instr_read_data_r0_r1;
dpm->bpwp_enable = cortex_a_bpwp_enable;
dpm->bpwp_disable = cortex_a_bpwp_disable;