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target/armv7m: rework Cortex-M register handling part 3

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Move primask/basepri/faultmask/control packing/unpacking from
cortex_m.c and hla_target.c to armv7m.c armv7m_read_core_reg()
and armv7m_write_core_reg() where also the FP 32/64-bit registers
conversion takes place.

Introduce a new hidden register ARMV7M_PMSK_BPRI_FLTMSK_CTRL
for packing/unpacking of special registers in the register cache.

The new packing/unpacking is endianess safe.

While on it improve returned error codes and LOG_ messages.

Just minimal changes in cortex_m.c and hla_target.c, will be
consolidated in the next patch.

Change-Id: Id51e764e243e54b5fdaadf2a202eee7c4bc729fe
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5863
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Tomas Vanek
2020-10-14 20:23:50 +02:00
committed by Antonio Borneo
parent e4160bd422
commit d3a37b0e76
4 changed files with 170 additions and 176 deletions
Download Patch File Download Diff File Expand all files Collapse all files

67
src/target/cortex_m.c
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@@ -1646,35 +1646,12 @@ static int cortex_m_load_core_reg_u32(struct target *target,
(int)(regsel - ARMV7M_REGSEL_S0), *value);
break;
case ARMV7M_PRIMASK:
case ARMV7M_BASEPRI:
case ARMV7M_FAULTMASK:
case ARMV7M_CONTROL:
/* Cortex-M3 packages these four registers as bitfields
* in one Debug Core register. So say r0 and r2 docs;
* it was removed from r1 docs, but still works.
*/
cortexm_dap_read_coreregister_u32(target, value, ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL);
case ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL:
retval = cortexm_dap_read_coreregister_u32(target, value, ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL);
if (retval != ERROR_OK)
return retval;
switch (regsel) {
case ARMV7M_PRIMASK:
*value = buf_get_u32((uint8_t *)value, 0, 1);
break;
case ARMV7M_BASEPRI:
*value = buf_get_u32((uint8_t *)value, 8, 8);
break;
case ARMV7M_FAULTMASK:
*value = buf_get_u32((uint8_t *)value, 16, 1);
break;
case ARMV7M_CONTROL:
*value = buf_get_u32((uint8_t *)value, 24, 3);
break;
}
LOG_DEBUG("load from special reg %" PRIu32 " value 0x%" PRIx32 "", regsel, *value);
LOG_DEBUG("load from special reg PRIMASK/BASEPRI/FAULTMASK/CONTROL value 0x%" PRIx32, *value);
break;
default:
@@ -1688,7 +1665,6 @@ static int cortex_m_store_core_reg_u32(struct target *target,
uint32_t regsel, uint32_t value)
{
int retval;
uint32_t reg;
struct armv7m_common *armv7m = target_to_armv7m(target);
switch (regsel) {
@@ -1728,37 +1704,10 @@ static int cortex_m_store_core_reg_u32(struct target *target,
(int)(regsel - ARMV7M_REGSEL_S0), value);
break;
case ARMV7M_PRIMASK:
case ARMV7M_BASEPRI:
case ARMV7M_FAULTMASK:
case ARMV7M_CONTROL:
/* Cortex-M3 packages these four registers as bitfields
* in one Debug Core register. So say r0 and r2 docs;
* it was removed from r1 docs, but still works.
*/
cortexm_dap_read_coreregister_u32(target, &reg, ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL);
case ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL:
cortexm_dap_write_coreregister_u32(target, value, ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL);
switch (regsel) {
case ARMV7M_PRIMASK:
buf_set_u32((uint8_t *)&reg, 0, 1, value);
break;
case ARMV7M_BASEPRI:
buf_set_u32((uint8_t *)&reg, 8, 8, value);
break;
case ARMV7M_FAULTMASK:
buf_set_u32((uint8_t *)&reg, 16, 1, value);
break;
case ARMV7M_CONTROL:
buf_set_u32((uint8_t *)&reg, 24, 3, value);
break;
}
cortexm_dap_write_coreregister_u32(target, reg, ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL);
LOG_DEBUG("write special reg %" PRIu32 " value 0x%" PRIx32 " ", regsel, value);
LOG_DEBUG("write special reg PRIMASK/BASEPRI/FAULTMASK/CONTROL value 0x%" PRIx32, value);
break;
default: