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- added a PLD (programmable logic device) subsystem for FPGA, CPLD etc. configuration

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- added support for loading .bit files into Xilinx Virtex-II devices
- added support for the Gateworks GW16012 JTAG dongle
- merged CFI fixes from XScale branch
- a few minor fixes


git-svn-id: svn://svn.berlios.de/openocd/trunk@116 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
drath
2006-11-22 13:03:10 +00:00
parent 03e8f264f4
commit e9297b40b9
16 changed files with 1641 additions and 76 deletions
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4
src/helper/binarybuffer.c
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@@ -143,8 +143,8 @@ int buf_cmp_mask(u8 *buf1, u8 *buf2, u8 *mask, int size)
/* mask out bits that don't really belong to the buffer if size isn't a multiple of 8 bits */
if ((size % 8) && (i == num_bytes -1 ))
{
if (((buf1[i] & ((1 << (size % 8)) - 1)) & ((1 << (size % 8)) - 1)) !=
((buf2[i] & ((1 << (size % 8)) - 1)) & ((1 << (size % 8)) - 1)))
if ((buf1[i] & ((1 << (size % 8)) - 1) & mask[i]) !=
(buf2[i] & ((1 << (size % 8)) - 1) & mask[i]))
return 1;
}
else