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target/armv7m: rework Cortex-M register handling part 1

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Define a new enum with DCRSR.REGSEL selectors.
Introduce armv7m_map_id_to_regsel() to unify mapping in one place.
Use DCRSR.REGSEL selectors for low level register read/write.

Change-Id: Ida0ccdfa9cdb1257a1900b8bfbf172b076374d39
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5327
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Christopher Head <chead@zaber.com>
This commit is contained in:
Tomas Vanek
2019-10-20 10:12:32 +02:00
committed by Antonio Borneo
parent f8453ae52c
commit efbc447ed8
4 changed files with 189 additions and 102 deletions
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64
src/target/cortex_m.c
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@@ -1607,29 +1607,25 @@ void cortex_m_enable_watchpoints(struct target *target)
}
static int cortex_m_load_core_reg_u32(struct target *target,
uint32_t num, uint32_t *value)
uint32_t regsel, uint32_t *value)
{
int retval;
/* NOTE: we "know" here that the register identifiers used
* in the v7m header match the Cortex-M3 Debug Core Register
* Selector values for R0..R15, xPSR, MSP, and PSP.
*/
switch (num) {
case 0 ... 18:
switch (regsel) {
case ARMV7M_REGSEL_R0 ... ARMV7M_REGSEL_PSP:
/* read a normal core register */
retval = cortexm_dap_read_coreregister_u32(target, value, num);
retval = cortexm_dap_read_coreregister_u32(target, value, regsel);
if (retval != ERROR_OK) {
LOG_ERROR("JTAG failure %i", retval);
return ERROR_JTAG_DEVICE_ERROR;
}
LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "", (int)num, *value);
LOG_DEBUG("load from core reg %" PRIu32 " value 0x%" PRIx32 "", regsel, *value);
break;
case ARMV7M_FPSCR:
case ARMV7M_REGSEL_FPSCR:
/* Floating-point Status and Registers */
retval = target_write_u32(target, DCB_DCRSR, 0x21);
retval = target_write_u32(target, DCB_DCRSR, ARMV7M_REGSEL_FPSCR);
if (retval != ERROR_OK)
return retval;
retval = target_read_u32(target, DCB_DCRDR, value);
@@ -1638,16 +1634,16 @@ static int cortex_m_load_core_reg_u32(struct target *target,
LOG_DEBUG("load from FPSCR value 0x%" PRIx32, *value);
break;
case ARMV7M_S0 ... ARMV7M_S31:
case ARMV7M_REGSEL_S0 ... ARMV7M_REGSEL_S31:
/* Floating-point Status and Registers */
retval = target_write_u32(target, DCB_DCRSR, num - ARMV7M_S0 + 0x40);
retval = target_write_u32(target, DCB_DCRSR, regsel);
if (retval != ERROR_OK)
return retval;
retval = target_read_u32(target, DCB_DCRDR, value);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("load from FPU reg S%d value 0x%" PRIx32,
(int)(num - ARMV7M_S0), *value);
(int)(regsel - ARMV7M_REGSEL_S0), *value);
break;
case ARMV7M_PRIMASK:
@@ -1658,9 +1654,9 @@ static int cortex_m_load_core_reg_u32(struct target *target,
* in one Debug Core register. So say r0 and r2 docs;
* it was removed from r1 docs, but still works.
*/
cortexm_dap_read_coreregister_u32(target, value, 20);
cortexm_dap_read_coreregister_u32(target, value, ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL);
switch (num) {
switch (regsel) {
case ARMV7M_PRIMASK:
*value = buf_get_u32((uint8_t *)value, 0, 1);
break;
@@ -1678,7 +1674,7 @@ static int cortex_m_load_core_reg_u32(struct target *target,
break;
}
LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
LOG_DEBUG("load from special reg %" PRIu32 " value 0x%" PRIx32 "", regsel, *value);
break;
default:
@@ -1689,51 +1685,47 @@ static int cortex_m_load_core_reg_u32(struct target *target,
}
static int cortex_m_store_core_reg_u32(struct target *target,
uint32_t num, uint32_t value)
uint32_t regsel, uint32_t value)
{
int retval;
uint32_t reg;
struct armv7m_common *armv7m = target_to_armv7m(target);
/* NOTE: we "know" here that the register identifiers used
* in the v7m header match the Cortex-M3 Debug Core Register
* Selector values for R0..R15, xPSR, MSP, and PSP.
*/
switch (num) {
case 0 ... 18:
retval = cortexm_dap_write_coreregister_u32(target, value, num);
switch (regsel) {
case ARMV7M_REGSEL_R0 ... ARMV7M_REGSEL_PSP:
retval = cortexm_dap_write_coreregister_u32(target, value, regsel);
if (retval != ERROR_OK) {
struct reg *r;
LOG_ERROR("JTAG failure");
r = armv7m->arm.core_cache->reg_list + num;
r = armv7m->arm.core_cache->reg_list + regsel; /* TODO: don't use regsel as register index */
r->dirty = r->valid;
return ERROR_JTAG_DEVICE_ERROR;
}
LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
LOG_DEBUG("write core reg %" PRIu32 " value 0x%" PRIx32 "", regsel, value);
break;
case ARMV7M_FPSCR:
case ARMV7M_REGSEL_FPSCR:
/* Floating-point Status and Registers */
retval = target_write_u32(target, DCB_DCRDR, value);
if (retval != ERROR_OK)
return retval;
retval = target_write_u32(target, DCB_DCRSR, 0x21 | (1<<16));
retval = target_write_u32(target, DCB_DCRSR, ARMV7M_REGSEL_FPSCR | DCRSR_WnR);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("write FPSCR value 0x%" PRIx32, value);
break;
case ARMV7M_S0 ... ARMV7M_S31:
case ARMV7M_REGSEL_S0 ... ARMV7M_REGSEL_S31:
/* Floating-point Status and Registers */
retval = target_write_u32(target, DCB_DCRDR, value);
if (retval != ERROR_OK)
return retval;
retval = target_write_u32(target, DCB_DCRSR, (num - ARMV7M_S0 + 0x40) | (1<<16));
retval = target_write_u32(target, DCB_DCRSR, regsel | DCRSR_WnR);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("write FPU reg S%d value 0x%" PRIx32,
(int)(num - ARMV7M_S0), value);
(int)(regsel - ARMV7M_REGSEL_S0), value);
break;
case ARMV7M_PRIMASK:
@@ -1744,9 +1736,9 @@ static int cortex_m_store_core_reg_u32(struct target *target,
* in one Debug Core register. So say r0 and r2 docs;
* it was removed from r1 docs, but still works.
*/
cortexm_dap_read_coreregister_u32(target, &reg, 20);
cortexm_dap_read_coreregister_u32(target, &reg, ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL);
switch (num) {
switch (regsel) {
case ARMV7M_PRIMASK:
buf_set_u32((uint8_t *)&reg, 0, 1, value);
break;
@@ -1764,9 +1756,9 @@ static int cortex_m_store_core_reg_u32(struct target *target,
break;
}
cortexm_dap_write_coreregister_u32(target, reg, 20);
cortexm_dap_write_coreregister_u32(target, reg, ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL);
LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
LOG_DEBUG("write special reg %" PRIu32 " value 0x%" PRIx32 " ", regsel, value);
break;
default: