diff --git a/tcl/target/st/stm32mp15x.cfg b/tcl/target/st/stm32mp15x.cfg
index bcdda73e9..979a5a491 100644
--- a/tcl/target/st/stm32mp15x.cfg
+++ b/tcl/target/st/stm32mp15x.cfg
@@ -18,6 +18,17 @@ if { [info exists CHIPNAME] } {
 	set _CHIPNAME stm32mp15x
 }
 
+# Set to 0 to prevent CPU examine. Default examine them
+if { ! [info exists EN_CA7_0] } {
+	set EN_CA7_0 1
+}
+if { ! [info exists EN_CA7_1] } {
+	set EN_CA7_1 1
+}
+if { ! [info exists EN_CM4] } {
+	set EN_CM4   1
+}
+
 if { [info exists CPUTAPID] } {
 	set _CPUTAPID $CPUTAPID
 } else {
@@ -42,20 +53,21 @@ if { [using_jtag] } {
 
 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap -ignore-syspwrupack
 
-# FIXME: Cortex-M code requires target accessible during reset, but this is not possible in STM32MP1
-# so defer-examine it until the reset framework get merged
 # NOTE: keep ap-num and dbgbase to speed-up examine after reset
 # NOTE: do not change the order of target create
 target create $_CHIPNAME.ap1 mem_ap -dap $_CHIPNAME.dap -ap-num 1
 target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2
 target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0
-target create $_CHIPNAME.cpu0 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 -dbgbase 0xE00D0000
-target create $_CHIPNAME.cpu1 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 1 -dbgbase 0xE00D2000
+target create $_CHIPNAME.cpu0 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 -dbgbase 0xE00D0000 -defer-examine
+target create $_CHIPNAME.cpu1 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 1 -dbgbase 0xE00D2000 -defer-examine
 target create $_CHIPNAME.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -defer-examine
 
 targets $_CHIPNAME.cpu0
 
 target smp $_CHIPNAME.cpu0 $_CHIPNAME.cpu1
+$_CHIPNAME.cpu0 configure -rtos hwthread
+$_CHIPNAME.cpu1 configure -rtos hwthread
+
 $_CHIPNAME.cpu0 cortex_a maskisr on
 $_CHIPNAME.cpu1 cortex_a maskisr on
 $_CHIPNAME.cpu0 cortex_a dacrfixup on
@@ -96,7 +108,16 @@ proc axi_nsecure {} {
 
 axi_secure
 
-proc dbgmcu_enable_debug {} {
+# mmw with target selection
+proc target_mmw {target reg setbits clearbits} {
+	set val [eval $target read_memory $reg 32 1]
+	set val [expr {($val & ~$clearbits) | $setbits}]
+	eval $target mww $reg $val
+}
+
+lappend _telnet_autocomplete_skip _enable_debug
+# Uses AP1
+proc _enable_debug {} {
 	# set debug enable bits in DBGMCU_CR to get ap2 and cm4 visible
 	catch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000007}
 	# freeze watchdog 1 and 2 on cores halted
@@ -104,30 +125,97 @@ proc dbgmcu_enable_debug {} {
 	catch {$::_CHIPNAME.ap1 mww 0xe008104c 0x00000008}
 }
 
-proc toggle_cpu0_dbg_claim0 {} {
-	# toggle CPU0 DBG_CLAIM[0]
-	$::_CHIPNAME.ap1 mww 0xe00d0fa0 1
-	$::_CHIPNAME.ap1 mww 0xe00d0fa4 1
+lappend _telnet_autocomplete_skip _handshake_with_wrapper
+# Uses AP1
+proc _handshake_with_wrapper { halt } {
+	set dbgmcu_cr 0
+	catch {set dbgmcu_cr [eval $::_CHIPNAME.ap1 read_memory 0xe0081004 32 1]}
+	if {[expr {($dbgmcu_cr & 0x07) == 0x00}]} {
+		echo "\nWARNING: FSBL wrapper not detected. Board in dev boot mode?\n"
+		return
+	}
+
+	if { $halt }  {
+		$::_CHIPNAME.ap1 arp_halt
+		if { $::EN_CA7_0 } {
+			$::_CHIPNAME.ap1 arp_halt
+			$::_CHIPNAME.ap1 mww 0xe00d0300 0
+			target_mmw $::_CHIPNAME.ap1 0xe00d0088 0x00004000 0
+		}
+	}
+
+	$::_CHIPNAME.ap1 mww 0xe0081004 0x7
 }
 
-proc detect_cpu1 {} {
+lappend _telnet_autocomplete_skip _detect_cpu1
+# Uses AP1
+proc _detect_cpu1 {} {
+	if { !$::EN_CA7_1 } {
+		return
+	}
+
 	set cpu1_prsr [$::_CHIPNAME.ap1 read_memory 0xE00D2314 32 1]
 	set dual_core [expr {$cpu1_prsr & 1}]
-	if {! $dual_core} {$::_CHIPNAME.cpu1 configure -defer-examine}
+	if { !$dual_core } {
+		set ::EN_CA7_1 0
+	}
 }
 
-proc rcc_enable_traceclk {} {
+lappend _telnet_autocomplete_skip _rcc_enable_traceclk
+proc _rcc_enable_traceclk {} {
 	$::_CHIPNAME.ap2 mww 0x5000080c 0x301
 }
 
 # FIXME: most of handler below will be removed once reset framework get merged
-$_CHIPNAME.ap1  configure -event reset-deassert-pre  {adapter deassert srst deassert trst;catch {dap init};catch {$::_CHIPNAME.dap apid 1}}
-$_CHIPNAME.ap2  configure -event reset-deassert-pre  {dbgmcu_enable_debug;rcc_enable_traceclk}
-$_CHIPNAME.cpu0 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu0 arp_examine}
-$_CHIPNAME.cpu1 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu1 arp_examine allow-defer}
-$_CHIPNAME.cpu0 configure -event reset-deassert-post {toggle_cpu0_dbg_claim0}
-$_CHIPNAME.cm4  configure -event reset-deassert-post {$::_CHIPNAME.cm4 arp_examine;if {[$::_CHIPNAME.ap2 curstate] == "halted"} {$::_CHIPNAME.cm4 arp_poll;$::_CHIPNAME.cm4 arp_poll;$::_CHIPNAME.cm4 arp_halt}}
-$_CHIPNAME.ap1  configure -event examine-start       {dap init}
-$_CHIPNAME.ap2  configure -event examine-start       {dbgmcu_enable_debug}
-$_CHIPNAME.cpu0 configure -event examine-end         {detect_cpu1}
-$_CHIPNAME.ap2  configure -event examine-end         {rcc_enable_traceclk;$::_CHIPNAME.cm4 arp_examine}
+$_CHIPNAME.cm4  configure -event reset-assert { }
+
+$_CHIPNAME.ap1  configure -event reset-assert-post {
+	adapter assert srst
+}
+
+$_CHIPNAME.ap1  configure -event reset-deassert-pre {
+	adapter deassert srst deassert trst
+	$::_CHIPNAME.ap1 arp_examine
+	_handshake_with_wrapper $halt
+	if { $::EN_CA7_0 } {
+		$::_CHIPNAME.cpu0 arp_examine
+		if { $halt } {
+			$::_CHIPNAME.cpu0 arp_halt
+		}
+	}
+	if { $::EN_CA7_1 } {
+		$::_CHIPNAME.cpu1 arp_examine
+		if { $halt } {
+			$::_CHIPNAME.cpu1 arp_halt
+		}
+	}
+	_enable_debug
+}
+
+$_CHIPNAME.ap2  configure -event reset-deassert-pre {
+	_rcc_enable_traceclk
+	if { $::EN_CM4 } {
+		$::_CHIPNAME.cm4 arp_examine
+		if { $halt } {
+			$::_CHIPNAME.cm4 arp_halt
+		}
+	}
+}
+
+$_CHIPNAME.ap1 configure -event examine-end {
+	_enable_debug
+	_detect_cpu1
+	if { $::EN_CA7_0 } {
+		$::_CHIPNAME.cpu0 arp_examine
+	}
+	if { $::EN_CA7_1 } {
+		$::_CHIPNAME.cpu1 arp_examine
+	}
+}
+
+$_CHIPNAME.ap2  configure -event examine-end {
+	_rcc_enable_traceclk
+	if { $::EN_CM4 } {
+		$::_CHIPNAME.cm4 arp_examine
+	}
+}