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flash: nand: align switch and case statements

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The coding style requires the 'case' to be at the same indentation
level of its 'switch' statement.

Align the code accordingly.

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	git log -p -w --ignore-blank-lines --patience

Change-Id: I9689e5b4650b8301d1b81e384e4db41b4efc3993
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9032
Tested-by: jenkins
This commit is contained in:
Antonio Borneo
2025-06-28 00:05:13 +02:00
parent 1042a8d179
commit f711ccfd7a
5 changed files with 234 additions and 234 deletions
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66
src/flash/nand/core.c
View File

@@ -310,15 +310,15 @@ int nand_probe(struct nand_device *nand)
retval = nand->controller->init(nand);
if (retval != ERROR_OK) {
switch (retval) {
case ERROR_NAND_OPERATION_FAILED:
LOG_DEBUG("controller initialization failed");
return ERROR_NAND_OPERATION_FAILED;
case ERROR_NAND_OPERATION_NOT_SUPPORTED:
LOG_ERROR("BUG: controller reported that it doesn't support default parameters");
return ERROR_NAND_OPERATION_FAILED;
default:
LOG_ERROR("BUG: unknown controller initialization failure");
return ERROR_NAND_OPERATION_FAILED;
case ERROR_NAND_OPERATION_FAILED:
LOG_DEBUG("controller initialization failed");
return ERROR_NAND_OPERATION_FAILED;
case ERROR_NAND_OPERATION_NOT_SUPPORTED:
LOG_ERROR("BUG: controller reported that it doesn't support default parameters");
return ERROR_NAND_OPERATION_FAILED;
default:
LOG_ERROR("BUG: unknown controller initialization failure");
return ERROR_NAND_OPERATION_FAILED;
}
}
@@ -449,18 +449,18 @@ int nand_probe(struct nand_device *nand)
/* erase size */
if (nand->device->erase_size == 0) {
switch ((id_buff[4] >> 4) & 3) {
case 0:
nand->erase_size = 64 << 10;
break;
case 1:
nand->erase_size = 128 << 10;
break;
case 2:
nand->erase_size = 256 << 10;
break;
case 3:
nand->erase_size = 512 << 10;
break;
case 0:
nand->erase_size = 64 << 10;
break;
case 1:
nand->erase_size = 128 << 10;
break;
case 2:
nand->erase_size = 256 << 10;
break;
case 3:
nand->erase_size = 512 << 10;
break;
}
} else
nand->erase_size = nand->device->erase_size;
@@ -469,18 +469,18 @@ int nand_probe(struct nand_device *nand)
retval = nand->controller->init(nand);
if (retval != ERROR_OK) {
switch (retval) {
case ERROR_NAND_OPERATION_FAILED:
LOG_DEBUG("controller initialization failed");
return ERROR_NAND_OPERATION_FAILED;
case ERROR_NAND_OPERATION_NOT_SUPPORTED:
LOG_ERROR("controller doesn't support requested parameters (buswidth: %i, address cycles: %i, page size: %i)",
nand->bus_width,
nand->address_cycles,
nand->page_size);
return ERROR_NAND_OPERATION_FAILED;
default:
LOG_ERROR("BUG: unknown controller initialization failure");
return ERROR_NAND_OPERATION_FAILED;
case ERROR_NAND_OPERATION_FAILED:
LOG_DEBUG("controller initialization failed");
return ERROR_NAND_OPERATION_FAILED;
case ERROR_NAND_OPERATION_NOT_SUPPORTED:
LOG_ERROR("controller doesn't support requested parameters (buswidth: %i, address cycles: %i, page size: %i)",
nand->bus_width,
nand->address_cycles,
nand->page_size);
return ERROR_NAND_OPERATION_FAILED;
default:
LOG_ERROR("BUG: unknown controller initialization failure");
return ERROR_NAND_OPERATION_FAILED;
}
}

84
src/flash/nand/davinci.c
View File

@@ -256,17 +256,17 @@ static int davinci_write_page(struct nand_device *nand, uint32_t page,
/* If we're not given OOB, write 0xff where we don't write ECC codes. */
switch (nand->page_size) {
case 512:
oob_size = 16;
break;
case 2048:
oob_size = 64;
break;
case 4096:
oob_size = 128;
break;
default:
return ERROR_NAND_OPERATION_FAILED;
case 512:
oob_size = 16;
break;
case 2048:
oob_size = 64;
break;
case 4096:
oob_size = 128;
break;
default:
return ERROR_NAND_OPERATION_FAILED;
}
if (!oob) {
ooballoc = malloc(oob_size);
@@ -391,15 +391,15 @@ static int davinci_write_page_ecc1(struct nand_device *nand, uint32_t page,
* for 16-bit OOB, those extra bytes are discontiguous.
*/
switch (nand->page_size) {
case 512:
oob_offset = 0;
break;
case 2048:
oob_offset = 40;
break;
default:
oob_offset = 80;
break;
case 512:
oob_offset = 0;
break;
case 2048:
oob_offset = 40;
break;
default:
oob_offset = 80;
break;
}
davinci_write_pagecmd(nand, NAND_CMD_SEQIN, page);
@@ -482,15 +482,15 @@ static int davinci_write_page_ecc4(struct nand_device *nand, uint32_t page,
* the standard ECC logic can't handle.
*/
switch (nand->page_size) {
case 512:
l = ecc512;
break;
case 2048:
l = ecc2048;
break;
default:
l = ecc4096;
break;
case 512:
l = ecc512;
break;
case 2048:
l = ecc2048;
break;
default:
l = ecc4096;
break;
}
davinci_write_pagecmd(nand, NAND_CMD_SEQIN, page);
@@ -741,19 +741,19 @@ NAND_DEVICE_COMMAND_HANDLER(davinci_nand_device_command)
info->read_page = nand_read_page_raw;
switch (eccmode) {
case HWECC1:
/* ECC_HW, 1-bit corrections, 3 bytes ECC per 512 data bytes */
info->write_page = davinci_write_page_ecc1;
break;
case HWECC4:
/* ECC_HW, 4-bit corrections, 10 bytes ECC per 512 data bytes */
info->write_page = davinci_write_page_ecc4;
break;
case HWECC4_INFIX:
/* Same 4-bit ECC HW, with problematic page/ecc layout */
info->read_page = davinci_read_page_ecc4infix;
info->write_page = davinci_write_page_ecc4infix;
break;
case HWECC1:
/* ECC_HW, 1-bit corrections, 3 bytes ECC per 512 data bytes */
info->write_page = davinci_write_page_ecc1;
break;
case HWECC4:
/* ECC_HW, 4-bit corrections, 10 bytes ECC per 512 data bytes */
info->write_page = davinci_write_page_ecc4;
break;
case HWECC4_INFIX:
/* Same 4-bit ECC HW, with problematic page/ecc layout */
info->read_page = davinci_read_page_ecc4infix;
info->write_page = davinci_write_page_ecc4infix;
break;
}
return ERROR_OK;

138
src/flash/nand/mx3.c
View File

@@ -256,23 +256,23 @@ static int imx31_command(struct nand_device *nand, uint8_t command)
}
switch (command) {
case NAND_CMD_READOOB:
command = NAND_CMD_READ0;
in_sram_address = MX3_NF_SPARE_BUFFER0; /* set read point for
* data_read() and
* read_block_data() to
* spare area in SRAM
* buffer */
break;
case NAND_CMD_READ1:
command = NAND_CMD_READ0;
/*
* offset == one half of page size
*/
in_sram_address = MX3_NF_MAIN_BUFFER0 + (nand->page_size >> 1);
break;
default:
in_sram_address = MX3_NF_MAIN_BUFFER0;
case NAND_CMD_READOOB:
command = NAND_CMD_READ0;
in_sram_address = MX3_NF_SPARE_BUFFER0; /* set read point for
* data_read() and
* read_block_data() to
* spare area in SRAM
* buffer */
break;
case NAND_CMD_READ1:
command = NAND_CMD_READ0;
/*
* offset == one half of page size
*/
in_sram_address = MX3_NF_MAIN_BUFFER0 + (nand->page_size >> 1);
break;
default:
in_sram_address = MX3_NF_MAIN_BUFFER0;
}
target_write_u16(target, MX3_NF_FCMD, command);
@@ -291,20 +291,20 @@ static int imx31_command(struct nand_device *nand, uint8_t command)
*/
sign_of_sequental_byte_read = 0;
switch (command) {
case NAND_CMD_READID:
mx3_nf_info->optype = MX3_NF_DATAOUT_NANDID;
mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
break;
case NAND_CMD_STATUS:
mx3_nf_info->optype = MX3_NF_DATAOUT_NANDSTATUS;
mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
break;
case NAND_CMD_READ0:
mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
break;
default:
mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
case NAND_CMD_READID:
mx3_nf_info->optype = MX3_NF_DATAOUT_NANDID;
mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
break;
case NAND_CMD_STATUS:
mx3_nf_info->optype = MX3_NF_DATAOUT_NANDSTATUS;
mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
break;
case NAND_CMD_READ0:
mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
break;
default:
mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
}
return ERROR_OK;
}
@@ -647,46 +647,46 @@ static int do_data_output(struct nand_device *nand)
struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
struct target *target = nand->target;
switch (mx3_nf_info->fin) {
case MX3_NF_FIN_DATAOUT:
/*
* start data output operation (set MX3_NF_BIT_OP_DONE==0)
*/
target_write_u16 (target, MX3_NF_CFG2,
MX3_NF_BIT_DATAOUT_TYPE(mx3_nf_info->optype));
{
int poll_result;
poll_result = poll_for_complete_op(target, "data output");
if (poll_result != ERROR_OK)
return poll_result;
case MX3_NF_FIN_DATAOUT:
/*
* start data output operation (set MX3_NF_BIT_OP_DONE==0)
*/
target_write_u16 (target, MX3_NF_CFG2,
MX3_NF_BIT_DATAOUT_TYPE(mx3_nf_info->optype));
{
int poll_result;
poll_result = poll_for_complete_op(target, "data output");
if (poll_result != ERROR_OK)
return poll_result;
}
mx3_nf_info->fin = MX3_NF_FIN_NONE;
/*
* ECC stuff
*/
if (mx3_nf_info->optype == MX3_NF_DATAOUT_PAGE
&& mx3_nf_info->flags.hw_ecc_enabled) {
uint16_t ecc_status;
target_read_u16 (target, MX3_NF_ECCSTATUS, &ecc_status);
switch (ecc_status & 0x000c) {
case 1 << 2:
LOG_DEBUG("main area read with 1 (correctable) error");
break;
case 2 << 2:
LOG_DEBUG("main area read with more than 1 (incorrectable) error");
return ERROR_NAND_OPERATION_FAILED;
}
mx3_nf_info->fin = MX3_NF_FIN_NONE;
/*
* ECC stuff
*/
if (mx3_nf_info->optype == MX3_NF_DATAOUT_PAGE
&& mx3_nf_info->flags.hw_ecc_enabled) {
uint16_t ecc_status;
target_read_u16 (target, MX3_NF_ECCSTATUS, &ecc_status);
switch (ecc_status & 0x000c) {
case 1 << 2:
LOG_DEBUG("main area read with 1 (correctable) error");
break;
case 2 << 2:
LOG_DEBUG("main area read with more than 1 (incorrectable) error");
return ERROR_NAND_OPERATION_FAILED;
}
switch (ecc_status & 0x0003) {
case 1:
LOG_DEBUG("spare area read with 1 (correctable) error");
break;
case 2:
LOG_DEBUG("main area read with more than 1 (incorrectable) error");
return ERROR_NAND_OPERATION_FAILED;
}
switch (ecc_status & 0x0003) {
case 1:
LOG_DEBUG("spare area read with 1 (correctable) error");
break;
case 2:
LOG_DEBUG("main area read with more than 1 (incorrectable) error");
return ERROR_NAND_OPERATION_FAILED;
}
break;
case MX3_NF_FIN_NONE:
break;
}
break;
case MX3_NF_FIN_NONE:
break;
}
return ERROR_OK;
}

148
src/flash/nand/mxc.c
View File

@@ -338,26 +338,26 @@ static int mxc_command(struct nand_device *nand, uint8_t command)
return validate_target_result;
switch (command) {
case NAND_CMD_READOOB:
command = NAND_CMD_READ0;
/* set read point for data_read() and read_block_data() to
* spare area in SRAM buffer
*/
if (nfc_is_v1())
in_sram_address = MXC_NF_V1_SPARE_BUFFER0;
else
in_sram_address = MXC_NF_V2_SPARE_BUFFER0;
break;
case NAND_CMD_READ1:
command = NAND_CMD_READ0;
/*
* offset == one half of page size
*/
in_sram_address = MXC_NF_MAIN_BUFFER0 + (nand->page_size >> 1);
break;
default:
in_sram_address = MXC_NF_MAIN_BUFFER0;
break;
case NAND_CMD_READOOB:
command = NAND_CMD_READ0;
/* set read point for data_read() and read_block_data() to
* spare area in SRAM buffer
*/
if (nfc_is_v1())
in_sram_address = MXC_NF_V1_SPARE_BUFFER0;
else
in_sram_address = MXC_NF_V2_SPARE_BUFFER0;
break;
case NAND_CMD_READ1:
command = NAND_CMD_READ0;
/*
* offset == one half of page size
*/
in_sram_address = MXC_NF_MAIN_BUFFER0 + (nand->page_size >> 1);
break;
default:
in_sram_address = MXC_NF_MAIN_BUFFER0;
break;
}
target_write_u16(target, MXC_NF_FCMD, command);
@@ -374,24 +374,24 @@ static int mxc_command(struct nand_device *nand, uint8_t command)
sign_of_sequental_byte_read = 0;
/* Handle special read command and adjust NF_CFG2(FDO) */
switch (command) {
case NAND_CMD_READID:
mxc_nf_info->optype = MXC_NF_DATAOUT_NANDID;
mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
break;
case NAND_CMD_STATUS:
mxc_nf_info->optype = MXC_NF_DATAOUT_NANDSTATUS;
mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
target_write_u16 (target, MXC_NF_BUFADDR, 0);
in_sram_address = 0;
break;
case NAND_CMD_READ0:
mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
break;
default:
/* Other command use the default 'One page data out' FDO */
mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
break;
case NAND_CMD_READID:
mxc_nf_info->optype = MXC_NF_DATAOUT_NANDID;
mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
break;
case NAND_CMD_STATUS:
mxc_nf_info->optype = MXC_NF_DATAOUT_NANDSTATUS;
mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
target_write_u16 (target, MXC_NF_BUFADDR, 0);
in_sram_address = 0;
break;
case NAND_CMD_READ0:
mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
break;
default:
/* Other command use the default 'One page data out' FDO */
mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
break;
}
return ERROR_OK;
}
@@ -857,20 +857,20 @@ static int ecc_status_v1(struct nand_device *nand)
target_read_u16(target, MXC_NF_ECCSTATUS, &ecc_status);
switch (ecc_status & 0x000c) {
case 1 << 2:
LOG_INFO("main area read with 1 (correctable) error");
break;
case 2 << 2:
LOG_INFO("main area read with more than 1 (incorrectable) error");
return ERROR_NAND_OPERATION_FAILED;
case 1 << 2:
LOG_INFO("main area read with 1 (correctable) error");
break;
case 2 << 2:
LOG_INFO("main area read with more than 1 (incorrectable) error");
return ERROR_NAND_OPERATION_FAILED;
}
switch (ecc_status & 0x0003) {
case 1:
LOG_INFO("spare area read with 1 (correctable) error");
break;
case 2:
LOG_INFO("main area read with more than 1 (incorrectable) error");
return ERROR_NAND_OPERATION_FAILED;
case 1:
LOG_INFO("spare area read with 1 (correctable) error");
break;
case 2:
LOG_INFO("main area read with more than 1 (incorrectable) error");
return ERROR_NAND_OPERATION_FAILED;
}
return ERROR_OK;
}
@@ -904,31 +904,31 @@ static int do_data_output(struct nand_device *nand)
struct target *target = nand->target;
int poll_result;
switch (mxc_nf_info->fin) {
case MXC_NF_FIN_DATAOUT:
/*
* start data output operation (set MXC_NF_BIT_OP_DONE==0)
*/
target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_DATAOUT_TYPE(mxc_nf_info->optype));
poll_result = poll_for_complete_op(nand, "data output");
if (poll_result != ERROR_OK)
return poll_result;
case MXC_NF_FIN_DATAOUT:
/*
* start data output operation (set MXC_NF_BIT_OP_DONE==0)
*/
target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_DATAOUT_TYPE(mxc_nf_info->optype));
poll_result = poll_for_complete_op(nand, "data output");
if (poll_result != ERROR_OK)
return poll_result;
mxc_nf_info->fin = MXC_NF_FIN_NONE;
/*
* ECC stuff
*/
if (mxc_nf_info->optype == MXC_NF_DATAOUT_PAGE && mxc_nf_info->flags.hw_ecc_enabled) {
int ecc_status;
if (nfc_is_v1())
ecc_status = ecc_status_v1(nand);
else
ecc_status = ecc_status_v2(nand);
if (ecc_status != ERROR_OK)
return ecc_status;
}
break;
case MXC_NF_FIN_NONE:
break;
mxc_nf_info->fin = MXC_NF_FIN_NONE;
/*
* ECC stuff
*/
if (mxc_nf_info->optype == MXC_NF_DATAOUT_PAGE && mxc_nf_info->flags.hw_ecc_enabled) {
int ecc_status;
if (nfc_is_v1())
ecc_status = ecc_status_v1(nand);
else
ecc_status = ecc_status_v2(nand);
if (ecc_status != ERROR_OK)
return ecc_status;
}
break;
case MXC_NF_FIN_NONE:
break;
}
return ERROR_OK;
}

32
src/flash/nand/tcl.c
View File

@@ -50,22 +50,22 @@ COMMAND_HANDLER(handle_nand_info_command)
int last = -1;
switch (CMD_ARGC) {
case 1:
first = 0;
last = INT32_MAX;
break;
case 2:
COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], i);
first = i;
last = i;
i = 0;
break;
case 3:
COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], first);
COMMAND_PARSE_NUMBER(int, CMD_ARGV[2], last);
break;
default:
return ERROR_COMMAND_SYNTAX_ERROR;
case 1:
first = 0;
last = INT32_MAX;
break;
case 2:
COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], i);
first = i;
last = i;
i = 0;
break;
case 3:
COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], first);
COMMAND_PARSE_NUMBER(int, CMD_ARGV[2], last);
break;
default:
return ERROR_COMMAND_SYNTAX_ERROR;
}
struct nand_device *p;