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Remove whitespace that occurs after '('.

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- Replace '([ \t]*' with '('.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2376 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
zwelch
2009-06-23 22:46:23 +00:00
parent 6d1d58a1fc
commit f90d8fa45f
69 changed files with 999 additions and 999 deletions
Download Patch File Download Diff File Expand all files Collapse all files

28
src/target/arm11.c
View File

@@ -709,7 +709,7 @@ int arm11_arch_state(struct target_s *target)
arm11_common_t * arm11 = target->arch_info;
LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name,
Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason )->name,
R(CPSR),
R(PC));
@@ -732,7 +732,7 @@ int arm11_halt(struct target_s *target)
arm11_common_t * arm11 = target->arch_info;
LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name );
if (target->state == TARGET_UNKNOWN)
{
@@ -789,7 +789,7 @@ int arm11_resume(struct target_s *target, int current, uint32_t address, int han
arm11_common_t * arm11 = target->arch_info;
LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name );
if (target->state != TARGET_HALTED)
@@ -889,7 +889,7 @@ int arm11_step(struct target_s *target, int current, uint32_t address, int handl
FNC_INFO;
LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name );
if (target->state != TARGET_HALTED)
{
@@ -1035,7 +1035,7 @@ int arm11_deassert_reset(struct target_s *target)
#if 0
LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name );
/* deassert reset lines */
@@ -1951,30 +1951,30 @@ int arm11_register_commands(struct command_context_s *cmd_ctx)
command_t * top_cmd = NULL;
RC_TOP( "arm11", "arm11 specific commands",
RC_TOP("arm11", "arm11 specific commands",
RC_TOP( "memwrite", "Control memory write transfer mode",
RC_TOP("memwrite", "Control memory write transfer mode",
RC_FINAL_BOOL( "burst", "Enable/Disable non-standard but fast burst mode (default: enabled)",
RC_FINAL_BOOL("burst", "Enable/Disable non-standard but fast burst mode (default: enabled)",
memwrite_burst)
RC_FINAL_BOOL( "error_fatal", "Terminate program if transfer error was found (default: enabled)",
RC_FINAL_BOOL("error_fatal", "Terminate program if transfer error was found (default: enabled)",
memwrite_error_fatal)
) /* memwrite */
RC_FINAL_BOOL( "no_increment", "Don't increment address on multi-read/-write (default: disabled)",
RC_FINAL_BOOL("no_increment", "Don't increment address on multi-read/-write (default: disabled)",
memrw_no_increment)
RC_FINAL_BOOL( "step_irq_enable", "Enable interrupts while stepping (default: disabled)",
RC_FINAL_BOOL("step_irq_enable", "Enable interrupts while stepping (default: disabled)",
step_irq_enable)
RC_FINAL( "vcr", "Control (Interrupt) Vector Catch Register",
RC_FINAL("vcr", "Control (Interrupt) Vector Catch Register",
arm11_handle_vcr)
RC_FINAL( "mrc", "Read Coprocessor register",
RC_FINAL("mrc", "Read Coprocessor register",
arm11_handle_mrc)
RC_FINAL( "mcr", "Write Coprocessor register",
RC_FINAL("mcr", "Write Coprocessor register",
arm11_handle_mcr)
) /* arm11 */

2
src/target/arm720t.c
View File

@@ -319,7 +319,7 @@ int arm720t_arch_state(struct target_s *target)
"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
"MMU: %s, Cache: %s",
armv4_5_state_strings[armv4_5->core_state],
Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name ,
Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason )->name ,
armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),

10
src/target/arm7_9_common.c
View File

@@ -526,7 +526,7 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
if ( watchpoint->mask != 0xffffffffu )
if (watchpoint->mask != 0xffffffffu )
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
@@ -543,7 +543,7 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
if ( watchpoint->mask != 0xffffffffu )
if (watchpoint->mask != 0xffffffffu )
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
@@ -974,7 +974,7 @@ int arm7_9_assert_reset(target_t *target)
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name);
Jim_Nvp_value2name_simple(nvp_target_state,target->state)->name);
enum reset_types jtag_reset_config = jtag_get_reset_config();
if (!(jtag_reset_config & RESET_HAS_SRST))
@@ -1044,7 +1044,7 @@ int arm7_9_deassert_reset(target_t *target)
{
int retval = ERROR_OK;
LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name);
Jim_Nvp_value2name_simple(nvp_target_state,target->state)->name);
/* deassert reset lines */
jtag_add_reset(0, 0);
@@ -1257,7 +1257,7 @@ int arm7_9_halt(target_t *target)
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name);
Jim_Nvp_value2name_simple(nvp_target_state,target->state)->name);
if (target->state == TARGET_HALTED)
{

2
src/target/arm7tdmi.c
View File

@@ -822,7 +822,7 @@ int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_
return ERROR_OK;
}
int arm7tdmi_target_create( struct target_s *target, Jim_Interp *interp )
int arm7tdmi_target_create(struct target_s *target, Jim_Interp *interp )
{
arm7tdmi_common_t *arm7tdmi;

2
src/target/arm920t.c
View File

@@ -497,7 +497,7 @@ int arm920t_arch_state(struct target_s *target)
exit(-1);
}
LOG_USER( "target halted in %s state due to %s, current mode: %s\n"
LOG_USER("target halted in %s state due to %s, current mode: %s\n"
"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
"MMU: %s, D-Cache: %s, I-Cache: %s",
armv4_5_state_strings[armv4_5->core_state],

2
src/target/arm926ejs.c
View File

@@ -547,7 +547,7 @@ int arm926ejs_arch_state(struct target_s *target)
"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
"MMU: %s, D-Cache: %s, I-Cache: %s",
armv4_5_state_strings[armv4_5->core_state],
Jim_Nvp_value2name_simple( nvp_target_debug_reason,target->debug_reason)->name,
Jim_Nvp_value2name_simple(nvp_target_debug_reason,target->debug_reason)->name,
armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),

2
src/target/arm966e.c
View File

@@ -110,7 +110,7 @@ int arm966e_init_arch_info(target_t *target, arm966e_common_t *arm966e, jtag_tap
return ERROR_OK;
}
int arm966e_target_create( struct target_s *target, Jim_Interp *interp )
int arm966e_target_create(struct target_s *target, Jim_Interp *interp )
{
arm966e_common_t *arm966e = calloc(1,sizeof(arm966e_common_t));

2
src/target/arm9tdmi.c
View File

@@ -39,7 +39,7 @@
int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
/* forward declarations */
int arm9tdmi_target_create( struct target_s *target, Jim_Interp *interp );
int arm9tdmi_target_create(struct target_s *target, Jim_Interp *interp );
int arm9tdmi_quit(void);

2
src/target/arm_adi_v5.h
View File

@@ -107,7 +107,7 @@ typedef struct swjdp_common_s
/* Accessor function for currently selected DAP-AP number */
static inline uint8_t dap_ap_get_select(swjdp_common_t *swjdp)
{
return (uint8_t)( swjdp ->apsel >> 24);
return (uint8_t)(swjdp ->apsel >> 24);
}
/* Internal functions used in the module, partial transactions, use with caution */

2
src/target/armv4_5.c
View File

@@ -299,7 +299,7 @@ int armv4_5_arch_state(struct target_s *target)
LOG_USER("target halted in %s state due to %s, current mode: %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
armv4_5_state_strings[armv4_5->core_state],
Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name,
Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason )->name,
armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));

2
src/target/armv7m.c
View File

@@ -462,7 +462,7 @@ int armv7m_arch_state(struct target_s *target)
armv7m_common_t *armv7m = target->arch_info;
LOG_USER("target halted due to %s, current mode: %s %s\nxPSR: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
Jim_Nvp_value2name_simple( nvp_target_debug_reason,target->debug_reason)->name,
Jim_Nvp_value2name_simple(nvp_target_debug_reason,target->debug_reason)->name,
armv7m_mode_strings[armv7m->core_mode],
armv7m_exception_string(armv7m->exception_number),
buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32),

2
src/target/armv7m.h
View File

@@ -144,7 +144,7 @@ extern int armv7m_blank_check_memory(struct target_s *target, uint32_t address,
* Rd: source register
* SYSm: destination special register
*/
#define ARMV7M_T_MSR(SYSm, Rn) ((0xF380 | ( Rn << 8 )) | ((0x8800 | SYSm) << 16))
#define ARMV7M_T_MSR(SYSm, Rn) ((0xF380 | (Rn << 8 )) | ((0x8800 | SYSm) << 16))
/* Change Processor State. The instruction modifies the PRIMASK and FAULTMASK
* special-purpose register values (Thumb mode) 16 bit Thumb2 instruction

4
src/target/cortex_a8.c
View File

@@ -87,7 +87,7 @@ int cortex_a8_dcc_read(swjdp_common_t *swjdp, uint8_t *value, uint8_t *ctrl)
{
uint16_t dcrdr;
mem_ap_read_buf_u16( swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
*ctrl = (uint8_t)dcrdr;
*value = (uint8_t)(dcrdr >> 8);
@@ -98,7 +98,7 @@ int cortex_a8_dcc_read(swjdp_common_t *swjdp, uint8_t *value, uint8_t *ctrl)
if (dcrdr & (1 << 0))
{
dcrdr = 0;
mem_ap_write_buf_u16( swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
}
return ERROR_OK;

10
src/target/cortex_m3.c
View File

@@ -444,7 +444,7 @@ int cortex_m3_debug_entry(target_t *target)
LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
armv7m_mode_strings[armv7m->core_mode],
*(uint32_t*)(armv7m->core_cache->reg_list[15].value),
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name);
if (armv7m->post_debug_entry)
armv7m->post_debug_entry(target);
@@ -520,7 +520,7 @@ int cortex_m3_poll(target_t *target)
#if 0
/* Read Debug Fault Status Register, added to figure out the lockup when running flashtest.script */
mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
LOG_DEBUG("dcb_dhcsr 0x%x, nvic_dfsr 0x%x, target->state: %s", cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
LOG_DEBUG("dcb_dhcsr 0x%x, nvic_dfsr 0x%x, target->state: %s", cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name );
#endif
return ERROR_OK;
@@ -751,7 +751,7 @@ int cortex_m3_assert_reset(target_t *target)
int assert_srst = 1;
LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name );
enum reset_types jtag_reset_config = jtag_get_reset_config();
if (!(jtag_reset_config & RESET_HAS_SRST))
@@ -1491,7 +1491,7 @@ int cortex_m3_dcc_read(swjdp_common_t *swjdp, uint8_t *value, uint8_t *ctrl)
{
uint16_t dcrdr;
mem_ap_read_buf_u16( swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
*ctrl = (uint8_t)dcrdr;
*value = (uint8_t)(dcrdr >> 8);
@@ -1502,7 +1502,7 @@ int cortex_m3_dcc_read(swjdp_common_t *swjdp, uint8_t *value, uint8_t *ctrl)
if (dcrdr & (1 << 0))
{
dcrdr = 0;
mem_ap_write_buf_u16( swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
}
return ERROR_OK;

4
src/target/embeddedice.h
View File

@@ -108,7 +108,7 @@ extern int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, uint32_t time
/* If many embeddedice_write_reg() follow eachother, then the >1 invocations can be this faster version of
* embeddedice_write_reg
*/
static __inline__ void embeddedice_write_reg_inner( jtag_tap_t *tap, int reg_addr, uint32_t value)
static __inline__ void embeddedice_write_reg_inner(jtag_tap_t *tap, int reg_addr, uint32_t value)
{
static const int embeddedice_num_bits[]={32,5,1};
uint32_t values[3];
@@ -117,7 +117,7 @@ static __inline__ void embeddedice_write_reg_inner( jtag_tap_t *tap, int reg_add
values[1]=reg_addr;
values[2]=1;
jtag_add_dr_out( tap,
jtag_add_dr_out(tap,
3,
embeddedice_num_bits,
values,

2
src/target/etb.c
View File

@@ -387,7 +387,7 @@ static int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cm
return ERROR_FAIL;
}
tap = jtag_tap_by_string( args[1] );
tap = jtag_tap_by_string(args[1] );
if (tap == NULL)
{
command_print(cmd_ctx, "Tap: %s does not exist", args[1] );

4
src/target/image.c
View File

@@ -533,7 +533,7 @@ static int image_mot_buffer_complete(image_t *image)
}
else if (record_type >= 1 && record_type <= 3)
{
switch ( record_type )
switch (record_type )
{
case 1:
/* S1 - 16 bit address data record */
@@ -636,7 +636,7 @@ static int image_mot_buffer_complete(image_t *image)
cal_checksum += (uint8_t)checksum;
bytes_read += 2;
if ( cal_checksum != 0xFF )
if (cal_checksum != 0xFF )
{
/* checksum failed */
LOG_ERROR("incorrect record checksum found in S19 file");

2
src/target/mips32.c
View File

@@ -265,7 +265,7 @@ int mips32_arch_state(struct target_s *target)
}
LOG_USER("target halted due to %s, pc: 0x%8.8" PRIx32 "",
Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name ,
Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason )->name ,
buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));
return ERROR_OK;

2
src/target/mips32_pracc.c
View File

@@ -207,7 +207,7 @@ static int mips32_pracc_exec_write(mips32_pracc_context *ctx, uint32_t address)
return ERROR_OK;
}
int mips32_pracc_exec( mips_ejtag_t *ejtag_info, int code_len, uint32_t *code, int num_param_in, uint32_t *param_in, int num_param_out, uint32_t *param_out, int cycle)
int mips32_pracc_exec(mips_ejtag_t *ejtag_info, int code_len, uint32_t *code, int num_param_in, uint32_t *param_in, int num_param_out, uint32_t *param_out, int cycle)
{
uint32_t ejtag_ctrl;
uint32_t address, data;

4
src/target/mips32_pracc.h
View File

@@ -35,7 +35,7 @@
#define UPPER16(uint32_t) (uint32_t >> 16)
#define LOWER16(uint32_t) (uint32_t & 0xFFFF)
#define NEG16(v) (((~(v)) + 1) & 0xFFFF)
/*#define NEG18(v) ( ((~(v)) + 1) & 0x3FFFF )*/
/*#define NEG18(v) (((~(v)) + 1) & 0x3FFFF )*/
extern int mips32_pracc_read_mem(mips_ejtag_t *ejtag_info, uint32_t addr, int size, int count, void *buf);
extern int mips32_pracc_write_mem(mips_ejtag_t *ejtag_info, uint32_t addr, int size, int count, void *buf);
@@ -53,6 +53,6 @@ extern int mips32_pracc_write_u32(mips_ejtag_t *ejtag_info, uint32_t addr, uint3
extern int mips32_pracc_read_regs(mips_ejtag_t *ejtag_info, uint32_t *regs);
extern int mips32_pracc_write_regs(mips_ejtag_t *ejtag_info, uint32_t *regs);
extern int mips32_pracc_exec( mips_ejtag_t *ejtag_info, int code_len, uint32_t *code, int num_param_in, uint32_t *param_in, int num_param_out, uint32_t *param_out, int cycle);
extern int mips32_pracc_exec(mips_ejtag_t *ejtag_info, int code_len, uint32_t *code, int num_param_in, uint32_t *param_in, int num_param_out, uint32_t *param_out, int cycle);
#endif

8
src/target/mips_m4k.c
View File

@@ -148,7 +148,7 @@ int mips_m4k_debug_entry(target_t *target)
LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s",
*(uint32_t*)(mips32->core_cache->reg_list[MIPS32_PC].value),
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name);
return ERROR_OK;
}
@@ -220,7 +220,7 @@ int mips_m4k_halt(struct target_s *target)
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name);
if (target->state == TARGET_HALTED)
{
@@ -265,7 +265,7 @@ int mips_m4k_assert_reset(target_t *target)
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name);
enum reset_types jtag_reset_config = jtag_get_reset_config();
if (!(jtag_reset_config & RESET_HAS_SRST))
@@ -324,7 +324,7 @@ int mips_m4k_assert_reset(target_t *target)
int mips_m4k_deassert_reset(target_t *target)
{
LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name);
/* deassert reset lines */
jtag_add_reset(0, 0);

616
src/target/target.c
View File

File diff suppressed because it is too large Load Diff

6
src/target/target.h
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@@ -396,8 +396,8 @@ int target_write_u8(struct target_s *target, uint32_t address, uint8_t value);
/* Issues USER() statements with target state information */
int target_arch_state(struct target_s *target);
void target_handle_event( target_t *t, enum target_event e);
void target_all_handle_event( enum target_event e );
void target_handle_event(target_t *t, enum target_event e);
void target_all_handle_event(enum target_event e );
#define ERROR_TARGET_INVALID (-300)
#define ERROR_TARGET_INIT_FAILED (-301)
@@ -412,6 +412,6 @@ void target_all_handle_event( enum target_event e );
#define ERROR_TARGET_NOT_EXAMINED (-311)
extern const Jim_Nvp nvp_error_target[];
extern const char *target_strerror_safe( int err );
extern const char *target_strerror_safe(int err );
#endif /* TARGET_H */

2
src/target/target_request.c
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@@ -117,7 +117,7 @@ int target_request(target_t *target, uint32_t request)
{
target_req_cmd_t target_req_cmd = request & 0xff;
if ( charmsg_mode ) {
if (charmsg_mode ) {
target_charmsg(target, target_req_cmd );
return ERROR_OK;
}

6
src/target/target_type.h
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@@ -129,16 +129,16 @@ struct target_type_s
int (*register_commands)(struct command_context_s *cmd_ctx);
/* called when target is created */
int (*target_create)( struct target_s *target, Jim_Interp *interp );
int (*target_create)(struct target_s *target, Jim_Interp *interp );
/* called for various config parameters */
/* returns JIM_CONTINUE - if option not understood */
/* otherwise: JIM_OK, or JIM_ERR, */
int (*target_jim_configure)( struct target_s *target, Jim_GetOptInfo *goi );
int (*target_jim_configure)(struct target_s *target, Jim_GetOptInfo *goi );
/* target commands specifically handled by the target */
/* returns JIM_OK, or JIM_ERR, or JIM_CONTINUE - if option not understood */
int (*target_jim_commands)( struct target_s *target, Jim_GetOptInfo *goi );
int (*target_jim_commands)(struct target_s *target, Jim_GetOptInfo *goi );
/* invoked after JTAG chain has been examined & validated. During
* this stage the target is examined and any additional setup is

2
src/target/trace.c
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@@ -123,7 +123,7 @@ static int handle_trace_history_command(struct command_context_s *cmd_ctx, char
uint32_t first = 0;
uint32_t last = trace->trace_history_pos;
if ( !trace->trace_history_size ) {
if (!trace->trace_history_size ) {
command_print(cmd_ctx, "trace history buffer is not allocated");
return ERROR_OK;
}

6
src/target/xscale.c
View File

@@ -959,7 +959,7 @@ int xscale_arch_state(struct target_s *target)
"MMU: %s, D-Cache: %s, I-Cache: %s"
"%s",
armv4_5_state_strings[armv4_5->core_state],
Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name ,
Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason )->name ,
armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
@@ -1202,7 +1202,7 @@ int xscale_halt(target_t *target)
xscale_common_t *xscale = armv4_5->arch_info;
LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name);
if (target->state == TARGET_HALTED)
{
@@ -1568,7 +1568,7 @@ int xscale_assert_reset(target_t *target)
xscale_common_t *xscale = armv4_5->arch_info;
LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name);
/* select DCSR instruction (set endstate to R-T-I to ensure we don't
* end up in T-L-R, which would reset JTAG