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- added support for Intel/Marvel PXA27x (XScale) targets

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- added support for scans coming from or ending in Shift-DR or Shift-IR to bitbang code (required for XScale debugging)
- cleaned up errror handlers. only use when there's a catchable error
- fix segfault when etm was configured without a valid driver



git-svn-id: svn://svn.berlios.de/openocd/trunk@176 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
drath
2007-06-21 13:15:22 +00:00
parent ee01d04908
commit ffb51c23fd
9 changed files with 126 additions and 128 deletions
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25
src/target/arm9tdmi.c
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@@ -104,7 +104,7 @@ int arm9tdmi_jtag_error_handler(u8 *in_value, void *priv)
DEBUG("caller: %s", caller);
return ERROR_OK;
return ERROR_JTAG_QUEUE_FAILED;
}
int arm9tdmi_examine_debug_reason(target_t *target)
@@ -117,7 +117,6 @@ int arm9tdmi_examine_debug_reason(target_t *target)
if ((target->debug_reason != DBG_REASON_DBGRQ)
&& (target->debug_reason != DBG_REASON_SINGLESTEP))
{
error_handler_t error_handler;
scan_field_t fields[3];
u8 databus[4];
u8 instructionbus[4];
@@ -156,9 +155,7 @@ int arm9tdmi_examine_debug_reason(target_t *target)
fields[2].in_handler_priv = NULL;
arm_jtag_scann(&arm7_9->jtag_info, 0x1);
error_handler.error_handler = arm9tdmi_jtag_error_handler;
error_handler.error_handler_priv = "arm9tdmi_examine_debug_reason";
arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, &error_handler);
arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
jtag_add_dr_scan(3, fields, TAP_PD, NULL);
jtag_execute_queue();
@@ -187,7 +184,6 @@ int arm9tdmi_examine_debug_reason(target_t *target)
/* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */
int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int sysspeed)
{
error_handler_t error_handler;
scan_field_t fields[3];
u8 out_buf[4];
u8 instr_buf[4];
@@ -204,10 +200,7 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s
jtag_add_end_state(TAP_PD);
arm_jtag_scann(jtag_info, 0x1);
error_handler.error_handler = arm9tdmi_jtag_error_handler;
error_handler.error_handler_priv = "arm9tdmi_clock_out";
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, &error_handler);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[0].device = jtag_info->chain_pos;
fields[0].num_bits = 32;
@@ -271,15 +264,11 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s
int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
{
scan_field_t fields[3];
error_handler_t error_handler;
jtag_add_end_state(TAP_PD);
arm_jtag_scann(jtag_info, 0x1);
error_handler.error_handler = arm9tdmi_jtag_error_handler;
error_handler.error_handler_priv = "arm9tdmi_clock_data_in_endianness";
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, &error_handler);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[0].device = jtag_info->chain_pos;
fields[0].num_bits = 32;
@@ -340,15 +329,11 @@ int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
{
scan_field_t fields[3];
error_handler_t error_handler;
jtag_add_end_state(TAP_PD);
arm_jtag_scann(jtag_info, 0x1);
error_handler.error_handler = arm9tdmi_jtag_error_handler;
error_handler.error_handler_priv = "arm9tdmi_clock_data_in_endianness";
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, &error_handler);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[0].device = jtag_info->chain_pos;
fields[0].num_bits = 32;