32e7a962c3
Write fence.i before dret.
...
Makes things work if the ROM doesn't contain fence.i (which is slow, so
Andrew took it out).
2016-09-23 14:16:23 -07:00
90f458e63f
Reading/writing s1 now works.
2016-09-23 14:16:23 -07:00
c364bd0ab5
We can run to a software breakpoint, but
...
gdb doesn't notice we're halted once we hit it, even though riscv_poll()
is setting the target state to halted.
2016-09-23 14:16:23 -07:00
dce4a992a3
Single memory reads/writes work.
2016-09-23 14:16:23 -07:00
1b349df638
WIP hackery.
...
Main thing I added is code to output "verilog" for every JTAG op we do,
so we can run the same thing in simulation.
2016-09-23 14:16:23 -07:00
9f22176618
Reading registers appears to work.
2016-09-23 14:16:23 -07:00
84944ded87
Fix up some register stuff.
...
Now you can attach with gdb, and it'll attempt to read a register. That
will fail because the core won't clear debug interrupt. Adding nops
doesn't help this time.
2016-09-23 14:16:23 -07:00
f634702aaf
Successfully determine xlen.
...
There's a nop in there for no reason, though.
2016-09-23 14:16:23 -07:00
482497c51a
Blind implementation of write_memory.
2016-09-23 14:16:22 -07:00
50ca8ac373
Blind implementation of read_memory.
2016-09-23 14:16:22 -07:00
76fe7db0db
In theory assert_reset/deassert_reset work.
2016-09-23 14:16:22 -07:00
ea6836c5f6
WIP, blind coding.
2016-09-23 14:16:22 -07:00
feff2dd9e7
Always leave the TAP in Run-Test/Idle.
2016-09-23 14:16:22 -07:00
98f2fa897f
Halt should work now.
2016-09-23 14:16:22 -07:00
Tim Newsome