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411 Commits

Author SHA1 Message Date
Megan Wachs 3fedb7d97f Merge remote-tracking branch 'origin/riscv' into HEAD 2018-04-18 15:22:38 -07:00
Tim Newsome 69a426038d Enforce OpenOCD style guide. (#239) 
* Enforce OpenOCD style guide.

Change-Id: I579a9f54ed22a774bf52f6aa5bc13bcbd2e82cd8

* Fail if `git diff` fails

Change-Id: I57256b0a24247f6123cb0e25a89c1b59867cb3f9

* Maybe every line gets its own shell?

Change-Id: I1a6f83e9f3d7cfd39f8933f0dba13c3cf76f71f6

* Maybe this will error properly.

Change-Id: I50803cfc229e61158569fb6b609195f7191ecac9

* Take different approach than merge-base

Change-Id: I345cbc4eecc4755c7127e8e36e403f7b727010b1

* Fix style issues.

Change-Id: I90e71f710858524812d0ab160b25c486b7b099e7
 2018-04-18 13:11:08 -07:00
Megan Wachs 8fa81c1f97 riscv-compliance... code that compiles > code that makes linter happy 2018-04-17 16:11:03 -07:00
Megan Wachs 8ce4f787ca riscv-compliance: whitespace cleanup 2018-04-17 16:05:15 -07:00
Megan Wachs 6217f56186 Merge remote-tracking branch 'origin/notice_reset' into riscv-compliance 2018-04-17 15:47:41 -07:00
Megan Wachs 401dcf7a06 riscv-compliance: make sure reset assertion and deassertion actually worked. 2018-04-17 15:47:15 -07:00
Megan Wachs f516825079 riscv-compliance: make sure not to clear DMACTIVE 2018-04-17 14:30:37 -07:00
Megan Wachs aef4888249 riscv-compliance: Fix writing hartsello 2018-04-17 11:55:50 -07:00
Megan Wachs 30e1dbdc6b riscv-compliance: fix compile errors and whitespace 2018-04-17 10:43:36 -07:00
Megan Wachs ef684c2e68 riscv-compliance: Incorporate feedback to make tests make fewer assumptions about hte implementation and properly use OpenOCD functions 2018-04-17 10:28:13 -07:00
Megan Wachs 716c12bcaf riscv: don't supporess errors 2018-04-17 07:57:32 -07:00
Megan Wachs 4c6c4cb078 riscv: Add a TODO note we need to handle hartselhi 2018-04-17 07:53:34 -07:00
Megan Wachs fa99b8e3b1 riscv-compliance: Fix OpenOCD lint checks 2018-04-17 07:49:06 -07:00
Megan Wachs bc32aaafa4 riscv-compliance: whitespace cleanup 2018-04-16 17:49:16 -07:00
Megan Wachs ff365173a0 riscv-compliance: fix too-narrow constant 2018-04-12 17:31:23 -07:00
Megan Wachs 2deff1b2c9 riscv: hartsel-> hartsello (not supporting hartselhi yet) 2018-04-12 16:10:45 -07:00
Megan Wachs 415da7ed4e riscv: update definitions to meet current version of spec 2018-04-12 16:06:30 -07:00
Megan Wachs adf7dd7b5e Merge branch 'riscv' into riscv-compliance 2018-04-12 16:03:54 -07:00
Megan Wachs 7eca2dfe5d Squashed commit of the following: 
commit fb7009fc38eff2f169385589e0f71ca4f9626cb2
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Fri Feb 23 16:41:14 2018 -0800

    Make some error messages to be printed once

commit e09dd62229bd2c152bf403e601aa098e29aaa850
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Fri Feb 23 15:30:10 2018 -0800

    Reduce severity of the error messages that are polluting the log

commit 73b6ea55ebefd004bef71359d611d3a887b89983
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Fri Feb 23 13:32:54 2018 -0800

    removed unused variable

commit c3bdcb0c4ae63bb5afad628c58eb29fe43c9646d
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Thu Feb 22 18:32:08 2018 -0800

    more R/O checks

commit 353cf212bd892bbb065e6a57fb9412cc8fea0548
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Thu Feb 22 14:27:25 2018 -0800

    write progbuf via DMI

commit e73d82e3d6cf064d0323e3c686f3b7710f42a51f
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Wed Feb 21 18:47:36 2018 -0800

    add writes to progbuf

commit f97e4b53e4064ae4e7807a1aac74c5d92aea7666
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Wed Feb 21 16:20:12 2018 -0800

    Try to zero out ROM
 2018-04-12 15:02:04 -07:00
Tim Newsome 6030644a9d Track misa per-hart even in -rtos mode 
This works around some side effects of the -rtos hack, namely that we
were unable to set hardware breakpoints on harts whose misa differed
from the first one. There may be other bugs like this one lurking
elsewhere. The only proper solution is for gdb to have a better user
interface when talking to a server that exposes multiple targets, but
that's a very big project.

This fixes #194.

Change-Id: I81aedddeaa922d220e936730e9c731545953ae21
 2018-04-03 15:12:19 -07:00
Tim Newsome eeae8c4261 Add gdb_report_register_access_error command 
This replaces the earlier mechanism which would propagate errors only
for targets that decided they wanted to. It was suggested by Matthias
Welwarsky from the OpenOCD team.

Change-Id: Ibe8e97644abb47aff26d74b8280377d42615a4d3
 2018-04-02 13:37:53 -07:00
Tim Newsome 755c6a4caa Add wall clock timeout to dmi_op() 
If the target is held in reset we'd keep adding more delays, and since
those grow exponentially they'd get so huge it would take forever to
exit out of the loop.

Change-Id: Ieaab8b124c101fd1b12f81f905a6de22192ac662
 2018-03-30 15:24:16 -07:00
Tim Newsome 58a2994b00 Merge pull request #231 from riscv/auth 
Fix auth error message.
 2018-03-30 14:02:29 -07:00
Tim Newsome 3c7c7e26a4 Merge pull request #230 from riscv/deleg 
Make m*deleg regs conditional on U/S/N
 2018-03-30 14:02:13 -07:00
Tim Newsome 4ee7d5373d Fix auth error message. 
Change-Id: I79b72325e9a6b85f8b67df8e9837a54cfce928f0
 2018-03-30 13:21:00 -07:00
Tim Newsome 224e7b4f16 Once more... Less sloppy this time. 
Change-Id: I4a24e777af3a0d8e072bc1bce0b314738393aa86
 2018-03-27 11:42:32 -07:00
Tim Newsome 55e427b72b Don't rely on havereset when deasserting reset. 
This removes the need for the supports_havereset config option as well.

Change-Id: Ic4391ce8c15d15e2ef662d170d483f336e8e8a5e
 2018-03-27 11:31:39 -07:00
Tim Newsome 0c05aafbf8 Fix m*deleg logic. 
Change-Id: Ieda035280334f8e7dc78c9fbc2bdbea7c565d2de
 2018-03-26 16:00:34 -07:00
Tim Newsome b6dca68b2e Make m*deleg regs conditional on U/S/N 
Change-Id: I544fc15625400d8ad64d4a65f0fc9d77f428ca84
 2018-03-23 13:43:12 -07:00
Tim Newsome c534a37fc3 Make reset work again for multicore 
Both regular multicore and RTOS hack methods.

Change-Id: I9a0998de0f33ef8a4d163f36ddf01c7675893b3d
 2018-03-23 12:53:24 -07:00
Tim Newsome d7282d0bfe Add set_supports_havereset 
This lets reset work on targets that don't implement havereset.

Change-Id: I09eb20970fac740eb6465541db6e739ae3e6b0d5
 2018-03-22 12:44:15 -07:00
Tim Newsome e5591c2584 Halt the target again if it was reset while halted 
Change-Id: I59707e7b2e1646c312d4eb8e96e9d7dfd1e128c2
 2018-03-20 12:34:17 -07:00
Tim Newsome 52eabbd2a5 Add riscv set_prefer_sba 
This allows a user to tell OpenOCD to prefer system bus access for
memory access, which can be useful for testing, or when there really is
a difference in behavior.

Change-Id: I8c2f15b89a2ccdae568c68ee743b75a74f9ad6bd
 2018-03-19 14:09:56 -07:00
Tim Newsome d5b450c508 Fix build, broken by b7c5c5d228. 
Change-Id: Iee55d799e14376ec5079d7db5fc6369e85368212
 2018-03-19 12:56:05 -07:00
Tim Newsome 40e0c5b976 Format error messages. 
Change-Id: I50c21319765e1ead279223466ed02a06ecf6a522
 2018-03-19 12:46:10 -07:00
Tim Newsome b7c5c5d228 Merge pull request #225 from riscv/old_bus2 
Support v0 System Bus Access
 2018-03-19 12:11:28 -07:00
Tim Newsome 4d2d1f7324 Notice when a hart has reset. 
Attempt to notify the user.
Deal correctly with a halted target that is suddenly running.

Change-Id: Ib0e0aa843d1da22df673713687ec884f6af14949
 2018-03-16 15:04:14 -07:00
Tim Newsome fd2759a63d Clear havereset in examine() and deassert_reset(). 
Change-Id: I89f32a44ebd6f3df0d0e2f6b54b111daa6ab06f7
 2018-03-16 15:03:31 -07:00
Tim Newsome 848062d0d1 Propagate errors in more places 
Change-Id: I5a7594d4b44c524537827f403348d0c10814546f
 2018-03-16 15:03:31 -07:00
Tim Newsome 3ddbbd525d Merge pull request #222 from riscv/dmi_commands 
Add riscv dmi_read/dmi_write commands.
 2018-03-15 11:32:33 -07:00
Tim Newsome 68a6812a41 Use TARGET_PRIxADDR instead of PRIx64. 
Change-Id: Iaf71a2d767ff4876b4cf1c9d546744ec6f97dda2
 2018-03-09 18:02:18 -08:00
Tim Newsome 075610d495 Support v0 system bus access 
This code was submitted at
https://github.com/riscv/riscv-openocd/pull/214. This change
incorporates that code, makes it build, and fixes the style to fit the
OpenOCD style guide.

I have not tested the new code because I don't have a target. It does
not cause any regressions.

Change-Id: Ic3639d822c887bd4a5517f044855fdd9d4e5a46d
 2018-03-09 18:02:18 -08:00
Tim Newsome fd9de02fac Merge pull request #221 from riscv/reg_running 
Error instead of asserting on reg access failure
 2018-03-07 12:22:33 -08:00
Tim Newsome c10c570dca Fix cut and paste error message. 
Change-Id: I1ff28278c6fc1b6dda1be53ca4f8ec2dd841b117
 2018-03-06 13:22:57 -08:00
Tim Newsome ddb894edf6 Add riscv dmi_read/dmi_write commands. 
Mostly addresses #207.

Also changed dmi_read() to return an error, and fixed all the call sites
to propagate that error if possible.

Change-Id: Ie6fd1f9e7eb46ff92cdb5021a7311ea7334904f1
 2018-03-06 12:45:55 -08:00
Tim Newsome 509e0e4715 Error instead of asserting on reg access failure 
Instead of asserting, return error when an abstract register access
fails on running target.

Fixes #201

Change-Id: I1ab3b31b0a4babf83c44f95ee2eeca92ef906d2f
 2018-03-02 20:24:58 -08:00
Tim Newsome 84c0fdd5d1 Don't always error if a debug program fails 
This is often expected, and the calling code should decide whether to
emit an error or not.

Change-Id: Ic21f38b4c75f01e6b40034fdc60dde6ba7a55f4a
 2018-03-02 20:02:32 -08:00
Tim Newsome 1d00d03dc0 Remove unable to read register error message 
It confuses users of IDEs like Eclipse, which request to read registers
that don't exist on the target.

Fixes #176

Change-Id: Ie2504140bfc70eba0d88fd763aacd87895aa20ff
 2018-03-02 19:41:31 -08:00
Tim Newsome 1d9418fbb0 Only propagate register errors on some targets 
Without this change, connecting to ARM targets is impossible.

Fixes #115.

Change-Id: Ie33c7e15ac1bed8c9cbd8e6a78de92d5498c5999
 2018-03-01 15:11:11 -08:00
Tim Newsome 0c8235d11f Merge pull request #216 from kaspar030/fix_some_fallthroughs 
target/riscv: add some switch fallthrough comments
 2018-02-28 12:31:22 -08:00