Report the 32-byte alignemnt requirement via the bank structure rather
than enforcing it ad-hoc in the write routine. This allows people to do
non-32-byte-aligned writes if they want, with the infrastructure fixing
up the addresses passed to the low-level driver.
Change-Id: I2c4f532f2000435954a900224dbc9f2c30d1cc94
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/5388
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Without this, a failed attempt to change option bytes will silently
appear to succeed but without actually changing the option bytes
(confusingly, the option bytes will still read back as if they had been
changed until a reboot as well!).
Change-Id: Id529c6c384a8a16be75f5702310670d99d8fac79
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/5418
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
We have the macro ARRAY_SIZE() already available. Use it!
Issue identified by checkpatch script from Linux kernel v5.1 using
the command
find src/ -type f -exec ./tools/scripts/checkpatch.pl \
-q --types ARRAY_SIZE -f {} \;
Change-Id: Ic7da9b710edf118eacb08f9e222f34208c580842
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5198
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
this is to avoid confusion with STM32 L4, L4+ and L5 families
also:
- a warning message is changed to error
- stm32l0x and stm32l1x aliases has been created to permit
the usage of either names
Change-Id: If3f16d2a3b7d1369959aa7407da37a9076ea91d7
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5437
Reviewed-by: Marc Schink <dev@zapb.de>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This will enable us to use either name when calling flash driver commands.
For example the stm32wbx family use the same flash driver as the stm32l4x, so
the user has to use 'stm32l4x lock 0' which can be confusing.
Now the user can also use 'stm32wbx lock 0' with the same result.
Change-Id: Ic0d8da9afc202d7cc82d9b9949827e958a1cc824
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5436
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Add driver for the RPC block in HF mode on Renesas R-Car Gen3 SoCs.
This driver allows operating the on-SIP HF memory.
Note that HF is CFI compliant flash, but it is not memory mapped,
hence the need to replace all the memory accessors and read/write
functions. The write function is entirely replaced to increase
performance and is Spansion/AMD specific, since there is no known
SIP with other HF from another vendor.
Add the following two lines to board TCL file to bind the driver on
R-Car Gen3 SoC using HyperFlash:
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME rpchf 0x08000000 0x4000000 2 2 $_CHIPNAME.a57.0
Change-Id: Ie18729d017eeb46e1363333ffe002d010dfc5ead
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/5149
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Fix comment of tested errors in asm src.
List all relevant errors in FLASH_ERROR mask: FLASH_PROGERR was missing
and any trial to re-program already programmed double word ended up
in the error bit held uncleared and flash write permanetly repeating
the error message until reset.
Lock the bank also after unsuccesfull write_block run.
Set async target algo block size to size of double word.
Remove warning in case of write_block success. In case of error
use LOG_ERROR instead of warning.
Change-Id: Ibf6d5e306a4c2eaa43de67d636b4902c737f02f3
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5360
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
The original code paded the write chunk with random bytes by overrunning
the buffer. An user can easily regard the random bytes to
be a programming error.
Change-Id: Ib0f47b5bc406bc6a7c32f3d929bf324a17c7c1e1
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5359
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
The chip->hwid is uint32_t , fix the print format.
This was detected by TravisCI on OSX, where this triggers a build error.
Change-Id: I776a7bb50e396c8fccc24500dec4750190da7982
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/5401
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Ilya Kharin <akscram@gmail.com>
Add driver for the SH QSPI controller. This SPI controller is often
connected to the boot SPI NOR flash on R-Car Gen2 platforms.
Add the following two lines to board TCL file to bind the driver on
R-Car Gen2 SoC and make SRAM work area available:
flash bank flash0 sh_qspi 0xe6b10000 0 0 0 ${_TARGETNAME}0 cs0
${_TARGETNAME}0 configure -work-area-phys 0xe6300000 -work-area-virt 0xe6300000 -work-area-size 0x10000 -work-area-backup 0
To install mainline U-Boot on the board, use the following procedure:
proc update_uboot {} {
# SPL
flash erase_sector 0 0x0 0x0
flash write_bank 0 /u-boot/spl/u-boot-spl.bin 0x0
# U-Boot
flash erase_sector 0 0x5 0x6
flash write_bank 0 /u-boot/u-boot.img 0x140000
}
Change-Id: Ief22f61e93bcabae37f6e371156dece6c4be3459
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
---
V2: - Add Makefile and linker script for the SH QSPI IO algorithm
- Include the algorithm code instead of hard-coding it
Reviewed-on: http://openocd.zylin.com/5143
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
This is a preparatory change, align the function name with the rest
of the API, no functional change.
Change-Id: I6a810d2a54edcd13ad9a87d24a7334802c41623b
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/5391
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This is a preparatory change, align the function name with the rest
of the API, no functional change.
Change-Id: Ib967520f027b03eb1792b36ede52335df8e23941
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/5390
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Add possibility to supply custom CFI memory accessors via cfi_info
and override the default memory-mapped ones.
Change-Id: I1b6bc1db69fc33e8cdef96c41742c40e6d8917e9
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/5147
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The size argument is always set to bank->bus_width and bank pointer
is now passed into cfi_target_{read,write}_memory(), so the size
can be accessed through the bank pointer inside the function instead
of being explicitly passed in.
Change-Id: I0abc1cc3bf513281c10cb5de7a21cb0e75cb7676
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/5389
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Replace passing in struct target with passing in struct flash_bank,
so that the later can contain function pointers to custom per-driver
memory accessor functions.
Change-Id: Id2573a6d5f1a73ed9c4f73c53592a9a335a11c99
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/5146
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
STM32L4P/Q devices have:
- similar flash layout as STM32L4R/S devices
- 1024K of flash memory (some parts have 512K only)
tested on NUCLEO-L4P5ZG using board/st_nucleo_l4.cfg
Change-Id: I77047351bc7dcd7c76d0f31a77be73005104a06f
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5392
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This rework is inspired from the 'flash/nor/stm32h7x.c'
This rework will ease the support of new devices on top of this driver:
for example: STM32WB have different flash base and size addresses
Notes:
- stm32l4_probe modified in order to charge the correct part_info from
the defined stm32l4_parts according to the device id
- stm32l4_flash_bank.bank2_start is replaced by .part_info->bank1_sectors
- STM32_FLASH_BASE is removed , part_info->flash_regs_base will be used instead
based on that flash register addresses are changed to offsets,
>> stm32l4_get_flash_reg was modified accordingly
- stm32l4_read_option and stm32l4_write_option was modified to accept an
offset instead of an absolute address, luckily this is the commands'
argument by default
- stm32l4_mass_erase modifications :
- use MER2 only on top of dual bank devices
- wait for BUSY bit before starting the mass erase
Change-Id: Ib35bfc3cbadc76bbeaaaba9005b82077b9e1e744
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/4932
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Create separate memory read/write functions which facilitate access
to the CFI NOR, so that they can be replaced by controller-specific
functions if necessary. This would become necessary when implementing
support for e.g. HyperFlash controllers, which do not directly map
the HyperFlash into the address space.
Change-Id: I1bba1edfd397cb37bfedb43efe2dd03feb26a375
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/5145
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Factor out the spansion unlock sequence to deduplicate the code.
Change-Id: Id78522e9a2f0e701870ef816772289d08257476a
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/5144
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The current code assumes an STM32's flash bank is laid-out in either of
two configurations:
- 4 x 16kB + 1 x 64kB + n x 128kB
- 4 x 32kB + 1 x 128kB + n x 256kB
This is quite ad-hoc but works fine in practice, as long as there are at
least 5 sectors (if n=0). Unfortunately, some newer STM32s are shipping
with only 64 kB of flash (4 x 16kB sectors).
This patch still assumes the same sector layout, but only keeps adding
sectors to the bank if the bank's capacity has not been reached. This
prevents openocd from crashing on some newer STM32s.
Change-Id: If00e5d7a328d11b399babc0bb2111e3ad8a3217e
Signed-off-by: Romain Goyet <romain.goyet@numworks.com>
Signed-off-by: Keir Fraser <keir.xen@gmail.com>
Reviewed-on: http://openocd.zylin.com/4926
Tested-by: jenkins
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
In commit cea40152f8 option bytes
reading was changed to direct access to option bytes area.
While there are no problems with stm32f0xx and stm32f3xx chips,
option block (0x1ffff800..0x1ffff80F) is unreadable from locked
stm32f10x chips.
As a result, stm32f1x unlock command writes dirty values to user
options, user data and write protection bits.
Option bytes reading reverted from direct access to option bytes area
to reading currently loaded bytes from FLASH_OBR/FLASH_WRPR registers.
Tested on stm32f100, stm32f103, stm32f107 as well as on stm32f030 and
stm32f303.
Change-Id: Iad476351ffdaca5ace12e02272dacea7f3d08f52
Signed-off-by: Oleksandr Redchuk <real@real.kiev.ua>
Reviewed-on: http://openocd.zylin.com/4940
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Use assert to remove "Dereference of null pointer" warnings.
Change-Id: Ie204c234a71758e6470351e1d9f22da3dd887f56
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5357
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
-fsize_base should be fsize_addr as it is the address of FLASH_SIZE register
-flash_base should be flash_regs_base to avoid confusion with flash block start
-add LOG_ERROR to functions stm32x_[read|write]_flash_reg(...)
Change-Id: I86f035314bcd616fc0bdf445692d945a85c15481
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5362
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Using a signed variable as a parameter of FLASH_SNB() macro
generated "warning: The result of the left shift is undefined
because the left operand is negative"
Change-Id: I8b3fe840f9308962460906097df6ddd848c07b25
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5356
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The new "Access control list" flash protection scheme used in nRF52840
is not yet supported. Do not prevent sector erase if protection
state is unknown.
Change-Id: Iae9a869a54ffbdc888fb3ec478dafb5c942d9ea0
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5348
Tested-by: jenkins
STM32H7x7 and STM32H7x5 devices contains two cores : CM7 + CM4
The second core creation is only done when
* DUAL_CORE variable is set to true
* non HLA interface is used
A second check for the second core existence is done in cpu1 examine-end
Once the second core is detected it gets examined.
Furthermore, the script provides a configurable CTI usage in order to halt
the cores simultaneously.
Tested on Rev X and V devices.
PS: the indentation was a mix of spaces and tabs, all changed to tabs.
Change-Id: Iad9c30826965ddb9be5dee628bc2e63f953bbcb8
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5130
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
functions managing option bytes cache (stm32x_read/write_options)
have bee removed, and a new functions to modify a single option byte
have been introduced (stm32x_write/modify_option).
by the way, some helpers have been introduced to access flash registers:
- stm32x_read_flash_reg(bank, offset, *value): int
- stm32x_write_flash_reg(bank, offset, value): int
and a new commands to read and write a single flash option register:
- stm32h7x option_read <bank> <option_reg offset>
- stm32h7x option_write <bank> <option_reg offset> <value> [mask]
also lock and unlock handlers' have been reduced by using the same routine
(stm32x_set_rdp) and have been optimized to not write options unless
there is a change in RDP level.
finally, several functions have been fixed to lock flash / options in case
of failure.
Change-Id: I75057949ab9f5b4e0f602bafb76f9f80d53a522b
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5293
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
To achieve that we need to avoid using FLASH_REG_BASE_B0, and use
bank registers instead:
For dual bank devices, each option register is mapped in 2 addresses
at the same offset from flash_bank_reg_base.
This is true for OPTCR, OPTKEYR, OPTSR_CUR/PRG, OPTCCR according to
RM0433 Rev6 (refer to section 3.9: FLASH registers)
In stm32x_write_options, according to RM0433 Rev6, after OBL launch we
should wait for OPTSR_CUR.BSY bit instead of FLASH_SR.QW
Change-Id: Ie24a91f069d03c9233797390fc2e925c737dad90
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5291
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Each bank had to store its options only, there is no need for bank1
to sneak into bank2 options.
Furthermore, some variants do not have a second bank.
Change-Id: I9229eb8ab4b5860ba2b0c5dbe626a54a84bca4d6
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5290
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Drop static pointer to allocated struct nrf5_info, iterate over
the flash bank list to find previously allocated nrf5 instances.
nrf5 is swd only device, so static allocation makes no harm,
but we should avoid copying the wrong code to other flash drivers.
Free sector array before allocating it to avoid memory leak on
re-probing device.
Change-Id: I781d8f4418a91c043f2393e5ecc5278fc6df3566
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4910
Tested-by: jenkins
Also refuse 'flash protect' on any nRF52.
Fail protection check on nRF52840 until ACL protection is implemented.
Change-Id: I84fcf117427e4894147c3ad92e2a3597566b4fcf
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4864
Tested-by: jenkins
nrf5 flash driver detected devices by looking up the HWID in the table
of known devices. Unfortunately chips are produced with many different
HWIDs for each type.
All nRF52 devices have FICR INFO field suitable for device identification
without need of HWID lookup.
Some newer nRF51 devices have FICR INFO too although undocumented.
Use this information to identify the device.
nrf5_info() is reworked to show just concise info.
Decoding FICR and UICR registers was moved from nrf5_info()
to a new command 'nrf5 info' without functional changes.
The flash bank for UICR page has the same size as program flash sector.
Change-Id: I900095b9ae23ee995f8e2bef8539b75d00300da5
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4848
Tested-by: jenkins
nRF5 flash controller can write a word at a time. Ask flash
infrastructure to handle alignment and padding.
Fix mixing of offset and address in nrf5_ll_flash_write()
- the original code worked just because NRF5_FLASH_BASE is 0
Change-Id: Ibe8bdf899a1764cf4117b2deda1a4618eeb16697
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4819
Tested-by: jenkins
Make driver_priv point directly into the corresponding chip bank structure
and add a pointer to it to get back to its chip when it's needed. This
removes the need to keep track of any bank number, either global or chip-
local.
In addition, it simplifies the cases where the chip structure was just used
to access the chip bank fields; now they are directly accessible.
Change-Id: Iaa353cd4fa7d8ff94c2ef69028c7cb32fade0420
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/4775
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The preverify option allows to check whether flashing is necessary.
If the target is flashed often/automatically this can save time and
preserve the flash. This is expecially helpful in CI environments.
Change-Id: Iead0a269e1a772b751d4dd9e8b53b2fecc874624
Signed-off-by: Moritz 'Morty' Strübe <moritz.struebe@redheads.de>
Reviewed-on: http://openocd.zylin.com/5292
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
