Commit Graph

6650 Commits

Author SHA1 Message Date
Megan Wachs 9a5a5c2dc9 Merge remote-tracking branch 'origin/reset-unexpected-check' into riscv-compliance 2018-05-16 22:29:45 -07:00
Megan Wachs 802c3b4003 riscv: remove unexpected check during reset
I'm not sure what this check is adding, and it causes problems for implementations that take some time to report that they are halted out of reset (e.g. by executing Debug ROM).
2018-05-16 22:25:38 -07:00
Megan Wachs efd7260972 Merge remote-tracking branch 'origin/riscv' into riscv-compliance 2018-05-14 07:31:25 -07:00
Tim Newsome 2a103bae44 Don't error if hart select isn't implemented.
It's not implemented for 0.11 because we don't need it. Returning error
caused 0.11 targets to not be debuggable since change
848062d0d1.

Change-Id: I8b04a1fcf3c3e8bf8340cbf39aaf475d2a213519
2018-05-07 15:16:57 -07:00
Tim Newsome 909c9d4ab2 Conform to OpenOCD style
Change-Id: I3954a8ac254b460560fa1414c5921777e4005645
2018-05-03 17:58:44 -07:00
Tim Newsome 487501e761 Merge branch 'riscv' into optimize
Change-Id: I2693eb05dee72acd2df5d8594c51e9da08ea1cc6
2018-05-03 16:02:59 -07:00
Tim Newsome 67b4e2c522 counter*h registers only exist on RV32
Fixes #245.

Change-Id: If05ec9773dc9975931434f09c431eba122a6e8d0
2018-05-03 12:26:30 -07:00
Tim Newsome 292180fb44 Merge pull request #246 from darius-bluespec/sysbus-bugfix
Bug fixes for system bus access
2018-05-01 14:12:48 -07:00
Darius Rad 31494f68a4 Properly retry system bus access if busy error was detected. 2018-05-01 11:45:24 -04:00
Darius Rad cb282e81bc Fix polling for system bus busy. 2018-05-01 11:45:24 -04:00
Tim Newsome b62c014bdc Merge branch 'riscv' into notice_reset 2018-04-30 13:36:06 -07:00
Megan Wachs 3715f207c0 fespi: flag an error if offset can't be handled in 3B mode 2018-04-24 10:24:01 -07:00
Tim Newsome 9a69c1c096 Fix mingw32 build.
Change-Id: If7a57749ba8c49385a4020ce8d2d8dbb94242122
2018-04-20 16:28:24 -07:00
Tim Newsome 4593659edf Fix error messages for reset dmi timeouts.
Change-Id: I00869ba20db6f27415af8e53e7b3e67741bf894d
2018-04-20 15:10:56 -07:00
Tim Newsome ba2174249d Make encoding.h pass style guide.
There's a manual step in commenting this out, but this file changes very
rarely.

Change-Id: I332d6490940ecc81e18c3b112a7ba415331b9c86
2018-04-20 14:47:27 -07:00
Tim Newsome b5dae238a1 Fix comments in encoding.h.
This was updated in the source a long time ago:
https://github.com/riscv/riscv-opcodes/commit/25881d8a221393cfd996ec074d8003ef31bfc5a6

Change-Id: Ia158205d046522c6802a3a32b330759f5e65566f
2018-04-20 14:47:27 -07:00
Megan Wachs eeac4f7fd4 riscv-compliance: remove whitespace 2018-04-19 10:52:19 -07:00
Megan Wachs debf2b040a riscv-compliance: correct the HALTSUM0/HALTSUM1 checks 2018-04-19 10:36:52 -07:00
Megan Wachs ac953c71c0 riscv-compliance: add dummy comments to appease the linter 2018-04-18 16:15:07 -07:00
Megan Wachs 06fc61f464 riscv-compliance: whitespace 2018-04-18 16:10:41 -07:00
Megan Wachs 3fedb7d97f Merge remote-tracking branch 'origin/riscv' into HEAD 2018-04-18 15:22:38 -07:00
Tim Newsome 005630d24d Use reset timeout to read dmstatus out of reset
Change-Id: I74cc6a1e006269270c5197994d21523d01206141
2018-04-18 14:31:00 -07:00
Tim Newsome 69a426038d Enforce OpenOCD style guide. (#239)
* Enforce OpenOCD style guide.

Change-Id: I579a9f54ed22a774bf52f6aa5bc13bcbd2e82cd8

* Fail if `git diff` fails

Change-Id: I57256b0a24247f6123cb0e25a89c1b59867cb3f9

* Maybe every line gets its own shell?

Change-Id: I1a6f83e9f3d7cfd39f8933f0dba13c3cf76f71f6

* Maybe this will error properly.

Change-Id: I50803cfc229e61158569fb6b609195f7191ecac9

* Take different approach than merge-base

Change-Id: I345cbc4eecc4755c7127e8e36e403f7b727010b1

* Fix style issues.

Change-Id: I90e71f710858524812d0ab160b25c486b7b099e7
2018-04-18 13:11:08 -07:00
Megan Wachs 8fa81c1f97 riscv-compliance... code that compiles > code that makes linter happy 2018-04-17 16:11:03 -07:00
Megan Wachs 8ce4f787ca riscv-compliance: whitespace cleanup 2018-04-17 16:05:15 -07:00
Megan Wachs 6217f56186 Merge remote-tracking branch 'origin/notice_reset' into riscv-compliance 2018-04-17 15:47:41 -07:00
Megan Wachs 401dcf7a06 riscv-compliance: make sure reset assertion and deassertion actually worked. 2018-04-17 15:47:15 -07:00
Megan Wachs f516825079 riscv-compliance: make sure not to clear DMACTIVE 2018-04-17 14:30:37 -07:00
Megan Wachs aef4888249 riscv-compliance: Fix writing hartsello 2018-04-17 11:55:50 -07:00
Megan Wachs 30e1dbdc6b riscv-compliance: fix compile errors and whitespace 2018-04-17 10:43:36 -07:00
Megan Wachs ef684c2e68 riscv-compliance: Incorporate feedback to make tests make fewer assumptions about hte implementation and properly use OpenOCD functions 2018-04-17 10:28:13 -07:00
Megan Wachs 716c12bcaf riscv: don't supporess errors 2018-04-17 07:57:32 -07:00
Megan Wachs 4c6c4cb078 riscv: Add a TODO note we need to handle hartselhi 2018-04-17 07:53:34 -07:00
Megan Wachs fa99b8e3b1 riscv-compliance: Fix OpenOCD lint checks 2018-04-17 07:49:06 -07:00
Megan Wachs bc32aaafa4 riscv-compliance: whitespace cleanup 2018-04-16 17:49:16 -07:00
Megan Wachs d673062291 Merge remote-tracking branch 'origin/style' into riscv-compliance 2018-04-16 17:31:18 -07:00
Megan Wachs ff365173a0 riscv-compliance: fix too-narrow constant 2018-04-12 17:31:23 -07:00
Megan Wachs 2deff1b2c9 riscv: hartsel-> hartsello (not supporting hartselhi yet) 2018-04-12 16:10:45 -07:00
Megan Wachs 415da7ed4e riscv: update definitions to meet current version of spec 2018-04-12 16:06:30 -07:00
Megan Wachs adf7dd7b5e Merge branch 'riscv' into riscv-compliance 2018-04-12 16:03:54 -07:00
Tim Newsome 836168be81 Fix FESPI assert when guessing few algorithm steps
Instead of trying to predict exactly how many steps will be required
(doable but error-prone), just allocate more memory when we need it.

Tested against HiFive1, and Arty board image.

Change-Id: I3cd9798432e65176616c700ba122daf7a5ed6209
2018-04-12 15:07:20 -07:00
Megan Wachs 7eca2dfe5d Squashed commit of the following:
commit fb7009fc38eff2f169385589e0f71ca4f9626cb2
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Fri Feb 23 16:41:14 2018 -0800

    Make some error messages to be printed once

commit e09dd62229bd2c152bf403e601aa098e29aaa850
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Fri Feb 23 15:30:10 2018 -0800

    Reduce severity of the error messages that are polluting the log

commit 73b6ea55ebefd004bef71359d611d3a887b89983
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Fri Feb 23 13:32:54 2018 -0800

    removed unused variable

commit c3bdcb0c4ae63bb5afad628c58eb29fe43c9646d
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Thu Feb 22 18:32:08 2018 -0800

    more R/O checks

commit 353cf212bd892bbb065e6a57fb9412cc8fea0548
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Thu Feb 22 14:27:25 2018 -0800

    write progbuf via DMI

commit e73d82e3d6cf064d0323e3c686f3b7710f42a51f
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Wed Feb 21 18:47:36 2018 -0800

    add writes to progbuf

commit f97e4b53e4064ae4e7807a1aac74c5d92aea7666
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Wed Feb 21 16:20:12 2018 -0800

    Try to zero out ROM
2018-04-12 15:02:04 -07:00
Tim Newsome 1fda89c3ce Only write hartsel if we're changing it.
DebugBreakpoint went from 2.94s to 2.74s.

Change-Id: Ia3ab857aea89fb83f0bcdd9a6bb69f256bde13dd
2018-04-09 15:13:24 -07:00
Tim Newsome 4b84e0d77b Remove prototype that crept back in.
Change-Id: I93c4690d6f655d2b4e5121cee889d9143d49b9ed
2018-04-09 12:51:20 -07:00
Tim Newsome c73e06809d Merge branch 'master' into from_upstream
Conflicts:
	src/rtos/rtos.c
	src/rtos/rtos.h
	src/server/gdb_server.c

Change-Id: Icd5a8165fe111f699542530c9cb034faf30e09b2
2018-04-09 12:17:08 -07:00
Tim Newsome 238b1e9f06 Cache registers while halted.
This saves us from re-reading s0 before doing just about anything
program buffer related.

Improves DebugBreakpoint from 3.01s to 2.89s. Feels like the improvement
should be larger than that. Maybe my metric isn't very good.

Change-Id: I85e1a1ddbf09006d76c451a32048be7b773dcfe9
2018-04-06 15:52:40 -07:00
Stefan Arnold be87994d60 flash/nor/at91samd: Add "nvmuserrow" command.
Add option "nvmuserrow" to "at91samd" for changing and reading the register at 0x804000 which represents various fuses.

Change-Id: I6382cc4ac15e6b9681e2f30b0ae60397a6289c3b
Signed-off-by: Stefan Arnold <sarnold@sh-sw.de>
Reviewed-on: http://openocd.zylin.com/4260
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-04-06 10:37:31 +01:00
Tim Newsome 5c0a9a9ee4 Just read abstractcs once when executing a command
DebugBreakpoint went from 3.41s to 3.05s!

Change-Id: Icfc4ad5fb663b3607bf2027fda744b43be662fc5
2018-04-05 17:59:07 -07:00
Tomas Vanek b08900badc nrf51: Add HWID 0x008F again
HWID originally added in commit 7829f31a6d
was accidentally omited during refactoring in commit
52885d2b53

While on it move old ingeneering sample of 51822 to block of 51822 rev 1

Change-Id: Ie9f15563792a27a72e71df6edbcc6b04490370ed
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4437
Tested-by: jenkins
2018-04-04 21:27:33 +01:00
Tomas Vanek 7829bb701f drivers/kitprog: workaround KitProg firmware bug of missing ZLP
KitProg firmware does not send a zero length packet at the end of the bulk-in
transmission of a length divisible by a bulk packet size. This is inconsistent
with the USB specification and results in jtag_libusb_bulk_read()
waits forever when a transmission of specific size is received.

Limit bulk read size to expected number of bytes for problematic tranfer sizes.
Use 1 second timeout as the last resort.

Change-Id: Ice80306424afd76e9fbc6851911ffd5109c84501
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4426
Tested-by: jenkins
Reviewed-by: Bohdan Tymkiv <bhdt@cypress.com>
2018-04-04 21:26:59 +01:00