Now you can attach with gdb, and it'll attempt to read a register. That
will fail because the core won't clear debug interrupt. Adding nops
doesn't help this time.
target_run_flash_async_algorithm() ignored abort from target
(rp set to 0) when raised after all data have been written in fifo.
I could result e.g. in not reported error during flash write.
The change adds rp test after target algorithm has finished.
Change-Id: Iadd93371e4a4602737be10079479285d81ae41b2
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3560
Tested-by: jenkins
Reviewed-by: Steven Stallion <stallion@squareup.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
- FPU detection and FPU register support added for Cortex-M7.
There is no apparent difference between FPv4 and FPv5_SP but ...
- Autoincrement range for MEM-AP added for Cortex-M7
This patch together with #3526 replaces #3123 except for stm32f7x.cfg.
Change-Id: I5ed5392e3835674160563ff37d67622a7bf2c877
Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-on: http://openocd.zylin.com/3531
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
If WAIT recovery fails (times out), an ABORT command is issued to the
DAP but under some conditions the SSTICKYORUN bit in CTRL/STAT is not
cleared as well, which renders the DP unusable. This happens when
trying to access e.g. the ROM table of powered-down cores, on many
targets.
Change-Id: Id0a7ba6180069eee562871314f520f938df9718f
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3476
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Allow using physical addresses with mem2array and array2mem. In order
to minimize the impact on existing scripts, "phys" is added as an
optional 5th parameter to both commands.
This patch also adds "phys" variants to the memwrite/memread commands
in memory.tcl.
Change-Id: Ia6307f9d861789e7f3ccf1f98961d666bf8d85d6
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3387
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Sometimes it is necessary to resume into a different state (ARM/Thumb)
than at debug state entry. According to the documentation this should
be possible with "arm core_state arm|thumb" before the resume command,
however the original code also restores the original CPSR, which
overrides whatever state the core was set to. This seems to work on some
cores (e.g. Cortex-A5) but not on others (e.g. Cortex-A9). Using the "BX"
instruction to set resume PC and core state works on Cortex-A9 and
ARM11, but is not sufficient on Cortex-A5, where an explicit write to
the PC (MOV pc, r0) is required additionally.
Change-Id: Ic03153b4b250fbb8cf6c75f8e329fb34829aa35f
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3386
Tested-by: jenkins
Reviewed-by: Alexander Stein <alexanders83@web.de>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
First, fix the timeval_ms() implementation to not have K&R but ANSI
argument semantics by adding a missing void.
timeval_ms() returns an int64_t, not uint64_t or long long. Consistently
use int64_t for variables and PRI*64 as format string.
While at it, change a few related variables to bool for clarity.
Note that timeval_ms() may return a negative error code, but not a
single caller checks for that.
Change-Id: I27cf83e75b3e9a8913f6c43e98a281bea77aac13
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3499
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
A developer tool: Direct access to AP registers can be useful
for handling vendor specific AP like Freescale Kinetis MDM or Atmel SMAP.
Change-Id: Ie2c7160fc6b2e398513eb23e1e52cbb52b88d9bd
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2777
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
Today the reset option for connect_assert_srst is not done for SWD.
This patch adds this to SWD and make it possible to connect to targets which might disable JTAG interface when running.
Change-Id: Ib89f7cf59b628e8f0b5fca9dd9e362e383c4b99f
Signed-off-by: Fredrik Hederstierna <fredrik@hederstierna.com>
Reviewed-on: http://openocd.zylin.com/3018
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The SAP in LS102x SoC's from Freescale is able to read and write to all
physical memory locations, independently of CPU cores and DAP.
This implementation is 100% based on reverse-engineering of JTAG
communication with an LS1021A SAP using a JTAG debugger with SAP support.
And as such, this code is for now "works-for-me", pending verification
by other OpenOCD users, or even better, actual information from Freescale
on the SAP interface.
Change-Id: Ibb30945e017894da5c402f9f633fc513bed4e68c
Signed-off-by: Esben Haabendal <esben@haabendal.dk>
Reviewed-on: http://openocd.zylin.com/3096
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tim Newsome